TSMC is building a PLP mass production system, which can significantly improve AI chip manufacturing efficiency

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Mars Finance reports that on June 15, according to etnews, TSMC will adopt the next-generation semiconductor packaging technology "Panel-Level Packaging (PLP)" to directly compete with Samsung Electronics. PLP can significantly improve the production efficiency of AI chips, and as TSMC accelerates preparations for mass production, the rivalry for dominance between it and Samsung Electronics, which has entered the market first, seems inevitable.
According to industry sources on the 15th, TSMC is building a materials, components, and equipment (MCE) supply chain to establish its PLP mass production system. Currently, TSMC is in discussions with domestic and international MCE companies regarding equipment investments. It is reported that TSMC plans to start PLP mass production as early as next year, which is seen as a substantial step toward this goal.
PLP is a technology that involves cutting finished circuit wafers into individual chips (dies) and then packaging them on rectangular panels to produce finished products. It contrasts with "Wafer-Level Packaging (WLP)" performed on circular wafers. When chips are packaged on circular wafers, the edge areas cannot be made into chips and must be discarded—this results in lower productivity. Packaging on rectangular panels allows for waste-free chip production. Based on a standard 600×600 mm rectangular panel, it can produce about five to six times the number of chips compared to the mainstream 300 mm (12-inch) wafers.
Currently, Samsung Electronics holds an advantage in PLP technology. After acquiring the PLP business from Samsung Electro-Mechanics in 2019, Samsung Electronics has continuously built its technical capabilities by applying this technology to mobile application processors (AP) and power management ICs (PMIC).
In contrast, TSMC had been relatively passive on PLP, relying on its traditional wafer-level packaging (WLP) to establish a competitive edge in the foundry industry. However, with the explosive growth of the AI chip market, the situation has reversed—PLP can increase AI chip output and facilitate the production of large-area AI chips. Therefore, TSMC has been actively promoting PLP business since 2024. It is expected that TSMC will build and operate a pilot production line this year, and after performance evaluation, it will enter large-scale mass production around next year.
Reportedly, TSMC has already secured a global AI chip customer.
As TSMC accelerates the mass production of PLP, competition with Samsung Electronics is expected to intensify further. Samsung also plans to expand the application scope of PLP from existing AP and PMIC to high-performance computing (HPC) chips, such as AI semiconductors. Additionally, glass substrates, which are highly regarded as AI chip substrates, are also likely to be used in this PLP process—this also indicates that Samsung Electronics and TSMC will compete for leadership in the next-generation substrate market.
An industry insider stated, "Not only Samsung Electronics and TSMC, but also many OSAT (Outsourced Semiconductor Assembly and Test) companies worldwide are entering the PLP process market," and added, "Intense competition is expected, and the market will also grow."
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