AIMPACT News, May 16 (UTC+8), Google disclosed the architecture details of the eighth-generation TPU (TPU 8t) rack-level connection to the Virgo network. The network uses high-radix switches and a flat two-layer non-blocking topology, increasing data center network bandwidth by four times compared to the previous generation, with a single structure capable of connecting over 134k TPU 8t chips, providing 47 Pb/s of non-blocking bidirectional bandwidth and nearly linear scaling performance of over 1.7K ExaFlops. The TPU 8t itself adopts a 3D torus topology, with a single super pod scalable to 9,600 chips, and supports expansion to over one million chips via JAX and Pathways. Key technologies include SparseCore accelerators, VPU/MXU overlap and balanced scaling, native FP4 support, and integrated Arm-based Axion CPUs to eliminate host bottlenecks. This design addresses the evolution of AI models from dense large language models to large-scale mixture-of-experts models and inference-intensive architectures. (Source: InFoQ)

View Original

This page may contain third-party content, which is provided for information purposes only (not representations/warranties) and should not be considered as an endorsement of its views by Gate, nor as financial or professional advice. See Disclaimer for details.

8 Likes

Reward
8
11
2
Share

Comment

Add a comment

MosaicBowtieRealm

· 10h ago

Single super pod 9600 chip, I counted the zeros, wow.

View OriginalReply0

LiquidityTeaMaster

· 05-27 04:44

The name “Virgo Network” is well chosen—its non-blocking, Virgo-style obsessive-compulsive mindset.

View OriginalReply0

ZkSketcher

· 05-27 03:08

Near-linear scaling to 1.7K ExaFlops, has Amdahl's Law failed at Google?

View OriginalReply0

MevBreakRoom

· 05-27 03:05

TPU 8t this bandwidth density is a bit outrageous, what does 47 Pb/s mean?

View OriginalReply0

NonceNinja

· 05-27 02:59

From JAX scaling to millions of chips, is Pathways finally going to have its moment?

View OriginalReply0

MarginMoth

· 05-27 02:57

High-capacity switches sound expensive, but they save optical modules compared to three-layer Clos.

View OriginalReply0

0xPeachy

· 05-27 02:54

After reading, I just want to ask: when will I be able to get the trial quota for TPU v6?

View OriginalReply0

SushiLatency

· 05-27 02:54

Arm Axion CPU integrated, heterogeneous computing is getting more and more sophisticated.

View OriginalReply0

Semi-MeltedIceCream

· 05-27 02:53

VPU/MXU overlap balancing, achieving this level of fine-grained scheduling is indeed impressive

View OriginalReply0

QuietExitPlan

· 05-27 02:52

134k chips in one structure, how to divide the fault domain is a matter of expertise

View OriginalReply0

Trending Topics
View More
#
StockTradingChallengeUpTo17000U
16.04M Popularity
#
GatePredictionMarketAddsSmartMoneyTracking
13.26M Popularity
#
USLaunchesNewStrikesOnIranOilRebounds
9.31M Popularity
#
TradeCFDWinGold
3.09M Popularity
#
DailyPolymarketHotspot
451.32K Popularity

Pinned

Sitemap

Google releases the eighth-generation TPU 8t rack-scale network architecture details

Trending Topics

StockTradingChallengeUpTo17000U

GatePredictionMarketAddsSmartMoneyTracking

USLaunchesNewStrikesOnIranOilRebounds

TradeCFDWinGold

DailyPolymarketHotspot

Pinned