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Google releases details of the eighth-generation TPU 8t rack-scale network architecture

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AIMPACT News, May 16 (UTC+8), Google disclosed the architecture details of the eighth-generation TPU (TPU 8t) rack-level connection to the Virgo network. The network uses high-radix switches and a flat two-layer non-blocking topology, increasing data center network bandwidth by four times compared to the previous generation, with a single structure capable of connecting over 134k TPU 8t chips, providing 47 Pb/s of non-blocking bidirectional bandwidth and nearly linear scaling performance of over 1.7K ExaFlops. The TPU 8t itself adopts a 3D torus topology, with a single super pod scalable to 9,600 chips, and supports expansion to over one million chips via JAX and Pathways. Key technologies include SparseCore accelerators, VPU/MXU overlap and balanced scaling, native FP4 support, and integrated Arm-based Axion CPUs to eliminate host bottlenecks. This design addresses the evolution of AI models from dense large language models to large-scale mixture-of-experts models and inference-intensive architectures. (Source: InFoQ)
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GateUser-bf5d0c14
· 1h ago
Rack interconnection using Virgo, flat two-layer non-blocking, this engineering detail is quite hardcore
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BlackVelvetKey
· 1h ago
SparseCore and FP4 native support, how much can training costs be reduced?
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AuroraSnowyWildernessSolitary
· 2h ago
47Pb/s non-blocking bandwidth is indeed outrageous; Google's network topology design must be aiming for AGI, right?
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GateUser-f78f1f3e
· 4h ago
Million-chip expansion, JAX/Pathways ecosystem binding is too deep in this wave
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CatUnderTheNeonBridge
· 5h ago
134,000 chip units single-structure—when AWS saw this scale, it went silent; when Azure saw it, it welled up with tears.
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AirdropJanitor
· 5h ago
Arm Axion CPU integration, TPU is also heading towards the SoC route
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AprDaydream
· 5h ago
MoE architecture-specific optimization, it looks like Gemini's next generation is going to do something big
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AirdropArchivist
· 5h ago
VPU/MXU Overlap Balancing, Google finally figured out how to schedule the compute units properly
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QuantitativeButNotPretentious
· 5h ago
Single super pod 9600 chip, how is the heat dissipation handled? Curious.
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