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Google releases the eighth-generation TPU 8t rack-scale network architecture details

MeNews
AIMPACT News, May 16 (UTC+8), Google disclosed the architecture details of the eighth-generation TPU (TPU 8t) rack-level connection to the Virgo network. The network uses high-radix switches and a flat two-layer non-blocking topology, increasing data center network bandwidth by four times compared to the previous generation, with a single structure capable of connecting over 134k TPU 8t chips, providing 47 Pb/s of non-blocking bidirectional bandwidth and nearly linear scaling performance of over 1.7K ExaFlops. The TPU 8t itself adopts a 3D torus topology, with a single super pod scalable to 9,600 chips, and supports expansion to over one million chips via JAX and Pathways. Key technologies include SparseCore accelerators, VPU/MXU overlap and balanced scaling, native FP4 support, and integrated Arm-based Axion CPUs to eliminate host bottlenecks. This design addresses the evolution of AI models from dense large language models to large-scale mixture-of-experts models and inference-intensive architectures. (Source: InFoQ)
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