τ-scaling + LogicFolding, shifting from transistor stacking to folding along the time dimension, this idea breaks free from the physical constraints of lithography machines.


381 chip models are in mass production, with an equivalent density of 14Å by 2031, and Kirin is adopting a new architecture—it's not about catching up, but about overtaking by changing lanes.
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Huawei proposes the τ scaling law, with Kirin chips first using LogicFolding this fall.
Huawei proposed the τ scaling law at ISCAS, advocating for replacing geometric scaling with time scaling, combined with device optimization, LogicFolding, parallel architectures, and UnifiedBus to achieve cross-layer breakthroughs.
A total of 381 chips have been mass-produced, and by 2031, high-end chips are expected to reach an equivalent transistor density of 14Å process technology, with Kirin chips adopting LogicFolding for the first time.
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