$AMD’s EPYC Venice CPUs have entered volume production, becoming the first HPC CPU product to ramp on TSMC’s 2nm process


Key points:
→ Venice is AMD’s 6th Gen EPYC CPU, based on Zen 6
→ It is expected to offer over 70% better performance and efficiency than the previous generation
→ Thread density should improve by over 30%
→ The top configuration could reach 256 cores and 512 threads, compared with Turin’s 192-core maximum
→ $AMD also plans to ramp Venice at TSMC Arizona, improving supply diversification
→ AMD’s broader roadmap includes Verano, an AI-focused CPU variant designed for agentic AI workflows, with support for newer memory standards like LPDDR
→ AMD is also using TSMC advanced packaging, including SoIC-X and CoWoS-L, across its AI and data center portfolio
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