Storage is wildly expanding capacity, and semiconductor equipment is entering a “super era”!

AI servers are reshaping the semiconductor equipment cycle. Demand for high-end storage is rising rapidly, with HBM and advanced DDR5 squeezing general-purpose storage capacity. Price increases, expansion of capital expenditures, and the release of equipment orders are starting to form the same main thread.

In a report dated July 9, an analyst from Guojin Securities’ machinery industry team, Wei Peng, wrote: “Global AI computing capacity and HBM storage capacity expansion are driving strong semiconductors equipment demand; growth certainty is especially prominent across both the back-end testing and the front-end wafer measurement tracks.” This means the market’s focus is not only on overall equipment volume expansion, but also on high-barrier steps such as testing and wafer measurement.

According to SEMI data, the global semiconductor equipment market size will grow from $116.6 billion in 2024 to $155.6 billion in 2027, with a compound growth rate of 10.1% from 2024 to 2027. Among them, testing equipment has higher elasticity: the market size is expected to rise from $7.6 billion in 2024 to $13.4 billion in 2027, with a compound growth rate of 21.1%.

The supply side is also amplifying cycle elasticity. Overseas equipment makers are constrained by shortages of core components and capacity saturation, pushing delivery cycles for mainstream front-end and storage supporting equipment to 12 to 24 months, with price increases showing up as well. Samsung, SK hynix, and others’ expansion schedules are constrained by equipment deliveries, while domestic equipment companies are simultaneously entering a window for domestic substitution and diversification of overseas customer procurement.

AI servers raise storage consumption, widening supply-demand gaps

The root source of this equipment cycle is that AI servers consume significantly more storage than traditional servers. Relevant calculations show that per AI server, the DRAM load is 8 to 10 times that of a traditional server, while NAND usage is about 3 times.

As demand rises, general-purpose storage supply is not releasing in step. Samsung and SK hynix allocate 80% to 90% of their advanced process capacity to HBM, while Micron shifts about 70% of capacity to HBM and high-end DDR5. The three major memory makers’ inventory is about 4 weeks, below the healthy safety inventory range of 8 to 12 weeks.

Prices are already responding. According to TrendForce data, the contract price of DDR5 in Q2 2026 is expected to rise quarter-over-quarter by 58% to 63%, while NAND Flash contract prices are expected to rise quarter-over-quarter by 70% to 75%; the HBM capacity gap is estimated at 50% to 60%.

The storage market is also expanding. The global storage chip market size was $192.9 billion in 2024, rising to $289.0 billion in 2025. It is expected to reach $377.5 billion in 2026, and is projected to reach $723.7 billion by 2030. The compound growth rate from 2025 to 2030 is 17.7%.

Memory makers ramp up capacity expansion, making equipment orders more “realizable”

Capital expenditures are a key metric for validating an equipment cycle.

According to TrendForce data, global DRAM capital expenditures will increase from $53.7 billion in 2025 to $61.3 billion in 2026, up 14%; NAND capital expenditures will rise from $21.1 billion in 2025 to $22.2 billion in 2026, up 5%. Samsung, SK hynix, and Micron’s combined 2026 capex is expected to reach $53.5 billion, up 16% from 2025.

Micron’s ramp-up efforts are the most pronounced. Its planned capex for 2026 is $27.0 billion, up 70.3% year-over-year. SK hynix’s capex increases in 2024 and 2025 were 65.8% and 75.5% year-over-year, respectively.

Domestic memory makers are also stepping up. ChangXin Tech’s revenue in 2024 was 24.18 billion yuan, up 166.1%; in the first three quarters of 2025, revenue was 32.08 billion yuan, up 97.8%. In terms of capex, ChangXin Tech invested 71.23 billion yuan in 2024, up 63.2% year-over-year.

The capacity expansions of ChangXin Tech and Yangtze Memory are more directly driving local equipment demand. ChangXin Tech plans to expand monthly production capacity by 50,000 to 60k wafers in 2026, corresponding to equipment procurement of about 35.0 billion to 43.0 billion yuan. Yangtze Memory’s Phase III project has entered equipment installation and commissioning; large-scale mass production is expected to start in the second half of 2026, corresponding to equipment procurement of about 20.0 billion yuan.

Overseas deliveries are lengthened, bringing two windows for domestic equipment

In 2026, the global supply lead times for semiconductor components are clearly lengthening. Automotive-grade 32-bit MCU lead times exceed 52 weeks, SiC lead times are 25 to 40 weeks, and analog IC lead times are 20 to 48 weeks.

Component shortages are inversely impacting equipment delivery. Overseas leading equipment companies such as Applied Materials and Tokyo Electron are constrained by core component shortages and capacity saturation, and some equipment delivery lead times are extended to 12 to 24 months.

This creates windows for domestic equipment makers. Domestic vendors already have product accumulation in steps such as etching, thin-film deposition, cleaning, and testing, making delivery efficiency and cost advantages more evident. Under expansion pressure, overseas wafer fabs begin engaging domestic suppliers, and markets such as Korea and Southeast Asia become potential incremental demand.

However, opportunities are not evenly distributed. Whether a company can obtain overseas validation, and whether it can enter repeat procurement, still depends on process stability, customer validation cycles, and delivery capability.

Domesticization shortcomings determine equipment cycle elasticity

Domestic semiconductor equipment localization rates are diverging clearly.

Cleaning equipment localization rates are already at 50% to 60%; etching equipment is 55% to 65%; CMP and thermal treatment are 30% to 40%. But high-barrier steps remain relatively low: PVD localization is 10% to 20%, CVD/ALD is 5% to 10%, photoresist coating and development is 5% to 10%, wafer inspection/measurement is only 1% to 10%, and lithography is 0% to 1%.

This is also why front-end wafer measurement and back-end testing have been placed in more important positions. They are not the largest steps in overall equipment volume, but they are the clearest areas where domestic substitution still faces shortfalls.

Domestic equipment companies’ R&D investment is rising. From 2020 to 2025, the total R&D spending of China’s semiconductor equipment firms increased from 3.31 billion yuan to 18.58 billion yuan; average R&D per company rose from 170 million yuan to 740 million yuan. Investment focuses on advanced packaging, HBM/DDR testing, lithography, electron-beam metrology, and high-end ion implantation, among other areas.

Order metrics are also improving. Innoel Technologies’ contract liabilities increased from 590 million yuan in 2020 to 3.04 billion yuan in 2025; Naura Technology’s contract liabilities rose from 130 million yuan to 4.85 billion yuan, and remain at 4.88 billion yuan in Q1 2026. Contract liabilities correspond to orders already signed but not yet delivered, indicating that domestic equipment adoption is no longer staying at the prototype stage.

Front-end wafer measurement is one of domestic equipment’s toughest shortcomings

Wafer measurement equipment runs through the front-end wafer fabrication flow, used to check indicators such as thin-film thickness, critical dimensions, and wafer surface defects. It is not simply a final check, but continuous process control during steps such as lithography, etching, and thin-film deposition, directly affecting yield.

According to SEMI statistics, wafer measurement equipment accounts for about 13% of the global semiconductor equipment market. QYResearch data shows that the global wafer measurement market size was about $19.22 billion in 2025, expected to reach $21.3 billion in 2026, and is projected to reach $32.1 billion by 2030. The compound growth rate from 2026 to 2030 is 10.8%.

Localization rates are only 1% to 10%. The reason is that high-precision hardware and software are controlled by overseas leading players, wafer fabs have long validation cycles, and customers are unwilling to switch easily; export controls further amplify supply-chain uncertainties.

Once domestic vendors pass validation, the value of subsequent repeat orders is higher. For storage, advanced processes, increased 3D NAND layer counts, and advanced packaging, all of these will add measurement demand.

Back-end FT testing is being re-priced

Among testing equipment, the tester is the core. In back-end testing equipment, the tester’s value share is about 63%; for storage testing, the share in the tester market is about 21%.

Storage testing equipment is almost monopolized by overseas leaders. In 2023, in the global storage test equipment market, Advantest held 56% market share, Teradyne 43%, and the two combined for 99%. Domestic companies previously mainly entered low- and mid-end storage testing and supporting equipment; high-end storage ATE complete systems remained a short板.

The importance of FT testing is rising. CP testing happens after wafer processing is completed and before packaging, mainly screening basic electrical parameters; FT testing happens after packaging, and in addition to basic electrical parameters, it also verifies system-level functions, dynamic parameters, timing characteristics, bandwidth and data rates, and signal integrity. It requires higher standards for number of channels, test frequency, high-speed signal handling capability, and timing accuracy.

Prices also reflect the gap. International high-end FT testers are priced above 11.0 million yuan per unit, higher than high-end CP testers at 9.0 million yuan per unit. QYResearch estimates that the global FT final test equipment market size is $3.84 billion in 2025, $4.1 billion in 2026, and $5.47 billion by 2030. The compound growth rate from 2026 to 2030 is 7.5%.

Huawei’s “Tao” law also pushes back-end value to a higher position. 3D stacking, Chiplet, hybrid bonding, and TSV mean chip performance no longer depends only on front-end geometric scaling; packaging and testing complexity increases, so back-end equipment is no longer just a supporting step.

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