“Tao’s Law” V2 is here—what new opportunities will the semiconductor industry chain have?

Recently, according to an open-access paper on ChinaXiv, the preprint platform of the Chinese Academy of Sciences, He Tingbo, Huawei's Director and President of the Semiconductor Business Unit, released version 2 of "A time scaling theory for multi-layer electronic systems" (referred to in the industry as the "Tau (τ) Law").

Compared to version V1 released on May 25, the new version retains the original theoretical framework and supplements a large amount of engineering implementation details, measured data, and product evolution roadmaps, further demonstrating the feasibility of the "Tau (τ) Law" as a new guiding principle for the development of the semiconductor industry.

The V2 version of the "Tau (τ) Law" paper has attracted widespread attention. As of press time, it has received over 270k views and more than 55k downloads.

From an investment opportunity perspective, institutional research reports indicate that the EDA (Electronic Design Automation) toolchain is crucial for the promotion of logic folding, and the EDA toolchain represents the biggest incremental opportunity from logic folding. In addition, companies in areas such as advanced packaging, wafers, and testing equipment are expected to benefit.

Disclosure of measured data for the new Kirin chip

The "Tau (τ) Law" proposes replacing "geometric scaling" with "time (τ) scaling" as a new guiding principle for the evolution of semiconductors and electronic systems—by continuously compressing signal propagation delays through innovative technologies such as logic folding, and continuously increasing transistor density, thereby enabling the sustained evolution of semiconductors and electronic systems.

According to the V2 paper, compared to the conventional planar design baseline used in the 2025 Kirin 9030 Pro chip, the 2026 Kirin adopts logic folding, achieving an increase in transistor density from 155MTr/mm² to 238MTr/mm² at the same process node—an improvement that previously required three years of geometric scaling to achieve. Under a supply voltage of 1.1V, the 2026 Kirin also sees a 13% increase in clock frequency to 3.1GHz. Compared to the Kirin 9030 Pro, under the same performance target at 25°C, the 2026 Kirin can reduce the supply voltage from 1.1V to 0.9V, with normalized power consumption dropping to 0.59, representing a 41% reduction in power consumption.

In May this year, He Tingbo stated in a media interview that under the "Tau (τ) Law," chip evolution can achieve "accelerated" development. This autumn, Huawei will release a new Kirin mobile chip, which will be the first complete "τ chip."

The V2 paper predicts that over the next decade, logic folding is expected to evolve from local critical path folding to comprehensive, multi-level folding—each package will integrate three, four, or even more active layers. From 2026 to 2035, transistor density is expected to move toward 400MTr/mm² and beyond.

At the same time, logic folding enables Kirin chips to significantly increase CPU core frequencies and paves the way for achieving 4GHz and higher frequencies.

The "Tau (τ) Law" provides a new path for an energy-efficient AI computing power foundation

The V1 paper of the Tau Law mentioned that from May 2020 to May 2026, Huawei Semiconductor designed and achieved mass production of 381 chips, serving fields such as mobile, AI, automotive, industrial, and infrastructure. Across the entire product portfolio, the τ scaling strategy has been consistently validated.

The "Tau (τ) Law" is also applicable in the field of artificial intelligence. The V2 paper elaborates on τ scaling in AI data centers. τ scaling in AI is achieved collaboratively across three levels: system architecture (unified bus), Hi-ONE optical interconnection, and topology reconfiguration of the package itself (3D folding). The V2 paper adds schematic diagrams to further explain the division of labor and collaboration among the three technologies: unified bus, Hi-ONE, and 3D folding.

In the paper, He Tingbo predicts that around 2030, the Ascend 990 will introduce logic folding into the AI accelerator field. Following this development path, hardware integration is expected to increase by more than 100 times by 2035, with τ scaling effects covering every layer of the stack, rather than being concentrated solely at the device level.

According to a research report from China Merchant Securities, the core value of Huawei's "Tau (τ) Law" in AI chip design lies in addressing the urgent need for high energy efficiency and high computing power density driven by the explosion of AI computing, through systematic architecture innovation rather than relying solely on process scaling. For AI computing infrastructure, the "Tau (τ) Law" responds to the core pain points of high data movement pressure and high energy costs in the era of large models, providing a sustainable development path for building a green, energy-efficient AI computing power foundation.

Institutions say the EDA toolchain is the biggest incremental opportunity

From an investment opportunity perspective, current EDA tools are developed for the planar design era, and institutions are optimistic about the EDA toolchain. According to a research report from BOCOM International, the main constraint on the comprehensive promotion of logic folding comes from the EDA toolchain. Current EDA tools were born in the era of two-dimensional chip design, and the requirements of logic folding are completely different. The EDA toolchain represents the biggest incremental opportunity from logic folding.

Furthermore, analysts say that the implementation of logic folding is highly dependent on advanced packaging. According to a research report from Central China Securities, logic folding can significantly improve chip performance. Logic folding needs to be based on advanced packaging technologies such as 2.5D/3D integration, hybrid bonding, TSV (Through Silicon Via), and Chiplet. Advanced packaging will become a core link affecting chip performance and is expected to drive rapid growth in advanced packaging and test equipment demand. Wafer fabs that support logic folding architectures are expected to see accelerated capacity release. Investment opportunities in domestic advanced packaging manufacturers, wafer fabs, and semiconductor equipment manufacturers are recommended.

Institutions predict that the PCB (Printed Circuit Board) segment is expected to benefit from the evolution of the Tau Law. According to a research report from Caixin Securities, PCBs, as key electronic interconnect components, not only provide electrical connections but also carry functions such as digital and analog signal transmission, power supply, and RF microwave signal transmission and reception. The evolution of the "Tau (τ) Law" is expected to further promote the high-end development of the PCB industry, strengthen the trend of high-density interconnect, accelerate the implementation of technologies such as vertical power delivery (VPD) and embedded components, and increase the added value and competitive barriers of PCB products.

(Editor: Wenjing)

Keywords:

                                                            Semiconductor