Intel is considering adopting a backside power delivery architecture in its 1.4nm process to catch up with TSMC and Samsung.

BlockBeats news, July 5, Intel is considering adopting an architecture that simultaneously utilizes front-side and back-side power delivery in its 1.4nm-class ultra-fine process to catch up with competitors.

Industry sources say that Intel originally planned to adopt the back-side power delivery dedicated technology PowerDirect in its 1.4nm-class baseline process 14A, but in the subsequent process 14A2, it is considering introducing a dual-side architecture that uses both front and back sides.

Intel previously announced plans to increase chip density by 1.3 times in the 14A process compared to 18A; the 14A process targets an M0 pitch of approximately 28nm, while the 14A2 process may advance the M0 pitch to 21nm through half-node improvements.

While maintaining the back-side power delivery network as the primary, Intel will reassign some front-side metal routing for auxiliary power and clock signal purposes to compensate for insufficient power margins caused by scaling and exposure limitations.

Intel's 14A process is planned to enter risk production in 2028 and mass production in 2029.

Intel needs to release the 14A process 0.9 version process design kit to external customers in October this year, and obtain confirmed orders from large fabless customers within the following 18 months.

In comparison, TSMC has already planned to ship genuine 1.4nm A14 products in 2028, and Samsung Electronics also plans to commercialize its 2nm improved process SF2Z using back-side power delivery technology in 2027.