Intel Bets on a "1.4nm Architecture Variant"… Reviewing Both Front Side and Back Side Power Delivery

Integrated device manufacturer (IDM) Intel has reportedly been considering, internally, an architecture that leverages both front side and back side power delivery in order to chase down its rivals at the 1.4nm class ultra fine node. According to the industry, Intel had planned to apply "PowerDirect," a back side power delivery (BSPDN) only technology, on 14A, the base process of the 1.4nm class. For the follow on 14A2 process, however, it is said to be reviewing the introduction of a "Dual side" architecture that uses both the front and back sides. This structural change is directly tied to the lithography limitation (stochastic defects) that emerges as the lowest metal interconnect (M0) pitch Intel is pursuing narrows to around 21nm.
Intel has officially announced a plan to raise chip density by 1.3 times versus its existing 18A in order to catch up with TSMC's N2/A14 and Samsung's SF2Z. The 14A process targets an M0 pitch of around 28nm, but through half node style improvements, 14A2 is analyzed to push the M0 pitch down to 21nm. In this case, even when lithography is performed twice (double patterning), the overall density gain is large enough that the economics of High NA EUV tools, which run into the hundreds of billions of won per unit, actually improve.
The problem is that once the circuit lines become extremely fine at 21nm or below, interconnect resistance rises exponentially. The nano through silicon via (nTSV) infrastructure originally built for back side power delivery cannot, on its own, handle the current density the transistors demand, producing an "IR drop" in which the voltage falls sharply. Accordingly, Intel is analyzed to have adopted a hybrid structure that keeps the back side power delivery network as the main path while reallocating part of the front side metal interconnect back to auxiliary power and clock signals, in order to secure the power margin that has grown insufficient due to scaling and lithography limits. Despite the downside of greater interconnect complexity, this is read as a "product of compromise," a backward variation of the architecture undertaken to squeeze out the 21nm process specifications.
Intel is short on time. Per its roadmap, 14A is scheduled to go through risk production in 2028 and enter volume production in 2029. To that end, Intel plans to distribute version 0.9 of the 14A process design kit (PDK) to external customers this October, and it now faces the task of locking in firm orders from major fabless customers within the next 18 months. By contrast, rival TSMC has already secured stable yields on its 2nm (N2) process across 2025 and 2026, completing its market entry in line with the product launch schedule of its largest customer, Apple. Moreover, by the time Intel begins 14A risk production in 2028, TSMC plans to have already shipped true 1.4nm (A14) finished products to the market. Samsung Electronics likewise plans to commercialize "SF2Z," an enhanced 2nm process applying back side power delivery, in 2027. Samsung's biggest weapon is the Gate All Around (GAA) transistor proficiency it has honed since first adopting the structure at the 3nm node.
An industry official explained, "While Intel is struggling to secure yields because it introduced GAA and BSPDN together for the first time at 20A/18A, Samsung is simply layering back side power delivery (BSPDN) on top of an already proven 2nm GAA structure, so its technical risk is far lower."
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