Huawei's first "Tao Chip" exudes an aura of dominance.

Over the weekend, He Tingbo, Huawei board member and president of the Semiconductor Business Unit, submitted the V2 version of "Time Microarchitecture Theory for Multi-Level Electronic Systems" on ChinaXiv, the preprint platform of the Chinese Academy of Sciences, which sparked strong attention from the global semiconductor industry and capital markets. As of the time of reporting, the paper has received 268.4k clicks and over 53.3k downloads.

The revision and update of a professional paper have garnered such widespread attention because the new version not only adds a large amount of engineering details and measured data to the theoretical framework, further demonstrating from a methodological perspective the feasibility of "Tao's Law" as a new principle guiding the development of the semiconductor industry in the post-Moore era, but also elaborates on the roadmap for the Kirin mobile chip and the Ascend AI computing platform over the next 5 to 10 years, providing the global semiconductor industry with a second sustainable development path beyond Moore's Law. This will have a significant impact on capital expenditure, orders, and capacity expansion in the industry chain.

Measured Data from Kirin Chips Validates the Practicality of Tao's Law

In the V1 version released on May 25, He Tingbo proposed a new principle for guiding the development of the semiconductor industry—Tao (τ) Law (hereinafter referred to as "Tao's Law"). The core of Tao's Law is to replace "geometric scaling" with "time (τ) scaling," using innovative technologies such as logic folding to continuously reduce signal propagation delay, thereby increasing transistor density and system performance, offering a Chinese solution for industrial development in the post-Moore era.

Unlike the V1 version, which mainly answered "what is Tao's Law," the V2 version integrates the related discussions into a complete system of eight chapters, adds key engineering definitions such as Gear Ratio, completes the engineering principles, and, for the first time, publicly discloses measured data from mass-produced chips, empirically demonstrating the feasibility of Tao's Law.

In a previous interview, He Tingbo stated that Huawei would release a new Kirin mobile phone chip in the fall of 2026, which would be the first complete "Tao chip."

In the new version of the "Tao's Law" paper, she revealed measured data from Huawei's new-generation Kirin chip, further verifying that Tao's Law is practical and economically feasible in terms of cost.

The new version of the paper mentions that through LogicFolding, Huawei's new-generation Kirin mobile SoC has achieved a 55% increase in transistor density at a fixed process node, while reducing power consumption by 41% under the same performance.

The new version of the paper discloses that compared to the Kirin 9030 Pro, which uses a traditional planar design as a baseline, the Kirin 2026 uses logic folding, increasing transistor density from 155 MTr/mm² to 238 MTr/mm²—an improvement that previously required three years of geometric scaling. Under a 1.1V supply voltage, the main frequency of the Kirin 2026 also increases by 13% to 3.1GHz; the SRAM operating frequency increases by more than 40%; the number of clock buffers is reduced by more than 50%, clock skew is reduced by 25%, and wire length is shortened by approximately 30%.

In the V2 version of the paper, He Tingbo predicts that over the next decade, logic folding is expected to evolve from local critical-path folding to comprehensive, multi-level folding—each package will integrate three, four, or even more active layers. This evolution is driven by low-temperature hybrid bonding technology (which relaxes thermal budget constraints between layers) and the gradual migration of through-silicon via (TSV) landing points from the top metal layer down to the M6 layer, which will free up more than 30% of high-level routing resources. From 2026 to 2035, transistor density is expected to advance toward 400 MTr/mm² and beyond.

The new version of the paper states that logic folding enables the Kirin chip to significantly increase CPU core frequency and paves the way for reaching 4 GHz and higher frequencies. The paper discloses the release plan for Kirin chips and the "evolution" trend of their CPU performance core operating frequencies.

Tao's Law Also Holds Great Potential in the AI Computing Domain

He Tingbo proposes in the paper that, in a large AI cluster, more than 80% of energy is consumed by data movement; more than 70% of system costs are used for data storage. Therefore, reducing the time data spends in transit—between chips, racks, and within the package—is at least as important as reducing the time spent on computation itself.

The V2 version of the paper also elaborates on τ scaling in AI data centers. The paper mentions that through a co-designed unified bus architecture incorporating memory semantics, near-package optical I/O, and edge-to-surface 3D folding technology, τ scaling can be achieved in AI computing systems: enabling large-scale AI clusters to operate as a single logical entity.

Huawei deputy chairman and rotating chairman Xu Zhijun previously disclosed that, in response to the explosive growth in demand for large model training and inference, Huawei is iterating its Ascend chips at a pace of "one generation per year, doubling computing power." This year, the Ascend 950PR has been released and exhibited, with significant improvements in interconnect bandwidth, self-developed HBM, and computing performance.

The new version of the paper also clarifies the evolution roadmap and timeline for Ascend chips: around 2030, the Ascend 990 will introduce logic folding into the AI accelerator category; by 2035, hardware integration is expected to increase by more than 100 times, with the reduction of τ distributed across every layer of the stack, rather than concentrated at the device level.

New Opportunities for the Semiconductor and AI Computing Industry Chain

In the V1 version of the paper, He Tingbo had already mentioned that between May 2020 and May 2026, Huawei HiSilicon designed and put 381 chips into mass production, serving the mobile, AI, automotive, industrial, and infrastructure markets. Across the entire product portfolio, the τ scaling argument has stood the test. Industry analysts believe that in the V2 version of the paper, Huawei has further validated the feasibility of the technical route with engineering details and a large amount of measured data, advancing Tao's Law from a "thought framework" to "engineering evidence," which will also accelerate the implementation of Tao's Law in the industry chain.

On the consumer electronics side, Huawei is about to officially release the Kirin 2026 flagship chip with complete logic folding technology. This is the first mass-produced "Tao's Law chip," expanding from a single layer to dual layers, with significant improvements in transistor density and other metrics. On the AI computing side, Huawei will iterate the next-generation Ascend AI chip within the year, equipped with 2.5D/3D stacking and Lingqu interconnect technology upgrade solutions. The Atlas 950 supernode based on Lingqu interconnect technology and the Ascend 950DT chip is expected to be available in the fourth quarter of 2026.

Beyond mobile phone chips and AI data centers, Huawei will also replicate logic folding technology to scenarios such as automotive chips, communication base station chips, and industrial control chips.

Industry chain sources expect that, in the coming period, Huawei will accelerate the expansion of hybrid bonding, 2.5D/3D packaging, and TSV process production lines by domestic packaging and testing manufacturers, and will gradually open up design specifications and interface standards for logic folding, prompting domestic EDA (Electronic Design Automation) companies to adapt 3D IC design tools and IP vendors to adapt to stacking architectures. Packaging and testing manufacturers are likely to enter a capacity expansion cycle, and demand and capacity utilization for domestic mature process wafer foundries will also rise, bringing new development opportunities for the entire semiconductor industry chain. The AI computing industry will also undergo restructuring. Over the next two to three years, China is expected to quickly catch up and achieve partial overtaking in the commercial deployment of large-scale AI computing clusters.

"The technological development framework for the next decade is now clear, yet many unresolved challenges remain that cannot be overcome by any single company. Areas such as tool chains, industry standards, performance benchmarks, device physics, and business models require collaborative co-creation across the entire industry," He Tingbo stated in the V2 version of the paper.

Source: Shanghai Securities News

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