τ Scaling: Huawei's new growth engine designed for the post-Moore era

Over the past 60 years, the semiconductor industry has driven progress by shrinking transistor sizes (Moore’s Law)—making chips smaller, denser, and cheaper.

But now, this route is no longer working:

Benefits have crashed for processes below 7nm.

Photolithography equipment costs are astronomical.

Design fees for a single chip in advanced processes exceed 1,000,000,000 (10 亿) USD.

The cost of an individual transistor is not falling—it’s rising.

Huawei’s semiconductor team used 6 years and 381 mass-produced chips to validate a new direction:

Stop chasing size—start chasing time.

They proposed the τ Scaling theory (τ Scaling):

Treat “time” as the core optimization metric, compress feature time τ across the entire stack—from transistor switching (picoseconds) to data-center tasks (seconds)—covering 12 orders of magnitude.

In simple terms:

Previously, it was about who could make things smaller; now, it’s about who can be faster, with lower latency and higher efficiency.

1. What exactly is τ Scaling?

τ is the delay / time constant at each layer, divided into four levels:

Transistors: switching speed

Circuits: signal transmission delay

Chips: compute and memory access delay

Systems: end-to-end communication synchronization time

The goal is to compress τ together across the full stack. Process, circuits, architecture, and systems all use the same set of metrics to optimize—no more optimizing in isolation.

2. Deployment on mobile: LogicFolding (logic folding)

Without upgrading the process, vertically stacking chips and using ultra-precise hybrid bonding to split critical paths across multiple layers is like giving the chip “stacked floors.”

Transistor density: from 155 to 238 million transistors per square millimeter per generation, a 55% increase

Energy efficiency: up 41%, with main clock frequency up nearly 13%

SRAM frequency: up more than 40%

Kirin 2026 targets a main clock frequency of 3.1GHz, with a 4GHz goal by 2029

3. Deployment in AI data centers: full-stack end-to-end delay compression

In an AI cluster, 80% of energy consumption and 70% of costs come from data movement; the key is compressing communication time.

1. Unified Bus

Cut multiple protocol layers. Remote access latency drops from dozens of microseconds to about 100 nanoseconds—500x faster.

2. Hi-ONE optical interconnect

Single module at 8Tb/s. Replace copper with fiber. Distance expands from 1 meter to 100 meters, supporting ten-thousand-card clusters.

3. 3D Folding

Fix the “area is growing fast, but interfaces can’t keep up” problem in 2.5D packaging by moving memory, power, and optical ports to the vertical dimension—synchronizing capacity scaling with compute scaling.

Prediction: by 2035, AI hardware integration will improve by more than 100 times

4. Re-fusing logic and memory

In the early years, CPUs and memory developed separately. Now in the AI era, data movement is more critical than computation, so memory and logic must be tightly integrated in 3D. The industry’s leverage in the value chain will shift toward memory and packaging.

5. Remaining challenges

EDA tools need to adapt to 3D stacked designs

Optimize process differences between wafers and losses from vertical interconnects

Support new energy-efficiency and Benchmark standards

Conclusion

The era of scaling by size under Moore’s Law has ended; the era of scaling by time has begun.

You don’t have to obsess over the most advanced lithography machines. By relying on 3D stacking, system architecture, and interconnect optimization, you can still continuously improve performance and energy efficiency.

This will be the core roadmap for semiconductors over the next 10 years.