Huawei proposes the τ scaling law, with Kirin chips first using LogicFolding this fall.

According to Beating Monitoring, Huawei will publish the τ scaling law at the 2026 IEEE International Conference on Circuits and Systems (ISCAS), proposing to replace geometric scaling with time scaling to find new paths for the evolution of chips and electronic systems. Based on the time scaling approach, Huawei has introduced the LogicFolding architecture and announced that the Kirin chips to be released in the fall of 2026 will adopt the LogicFolding architecture for the first time.

Traditional Moore’s Law depends on the continuous shrinking of transistor geometries, but advanced manufacturing processes are facing physical limits and diminishing cost-benefit returns. The core of the τ scaling law is to systematically shorten the propagation time of signals and data across devices, circuits, chips, and systems, thereby improving performance, energy efficiency, and equivalent transistor density.

At the device level, Huawei reduces the time constant τ by optimizing the resistance and parasitic capacitance of transistors and interconnects. At the circuit level, LogicFolding breaks through the boundaries of traditional circuit layout, shortens wiring on the critical path, and reduces the RC load of signal propagation. At the chip level, Huawei improves parallel efficiency through coordinated co-design of software, architecture, and chips. At the system level, the UnifiedBus interconnection protocol targets SuperPoD to achieve unified memory addressing and native memory semantics, reducing system communication latency.

Huawei claims that over the past 6 years, it has designed and mass-produced 381 chips based on the τ scaling law, covering scenarios such as mobile phones and AI computing. The company expects that by 2031, high-end chips designed based on the τ scaling law will reach 14 Å, equivalent to a 1.4 nm process transistor density. Huawei currently discloses the design approach and roadmap, but does not provide independent performance test data for LogicFolding on Kirin chips.