Understanding the Profit Pools and Industry Landscape of AI Storage Hierarchies in One Article

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Author: Godot

AI storage can be divided into six layers,

1. On-chip SRAM

2. HBM

3. Mainboard DRAM

4. CXL pooling layer

5. Enterprise SSD

6. NAS and cloud object storage

This hierarchy is based on the storage location; the further down, the farther from the compute unit, and the larger the storage capacity.

By 2025, these six layers (SRAM on compute chips, excluding embedded value) will total approximately $229 billion, with DRAM accounting for half, HBM 15%, and SSD 11%.

In terms of profit, each layer is extremely oligopolized, with the top three generally holding over 90% market share.

These profit pools can be divided into three categories,

1. High-margin oligopoly pools at the silicon chip level (HBM, embedded SRAM, QLC SSD)

2. High-margin emerging interconnect pools (CXL)

3. Scaled compound interest pools at the service level (NAS, cloud object storage)

The three pools differ in nature, growth rate, and moat.

Why is storage layered?

Because the CPUs responsible for control and the GPUs responsible for computation only have temporary cache, namely on-chip SRAM cache. This cache space is too small to hold large models.

Outside these chips, larger external memory is needed to store large models and inference contexts.

It’s very fast; data transfer between different storage layers introduces latency and energy consumption, which is the biggest issue.

Therefore, currently three directions are pursued,

1. Stack HBM, bringing memory close to the GPU to shorten transfer distances

2. CXL pooling, pooling memory at the rack level for shared capacity

3. Integrate compute and storage on the same wafer, combining storage and compute

These three directions will determine the shape of each profit pool over the next five years.

Below is a detailed layering,

L0 On-chip SRAM: TSMC’s exclusive profit pool

SRAM (Static Random-Access Memory) is the cache inside CPUs/GPUs, embedded in each chip, not traded separately.

The independent SRAM chip market is only about $1–1.7 billion, led by Infineon (~15%), Renesas (~13%), ISSI (~10%), a small market.

This profit pool is held by TSMC; each generation of AI chips requires more wafers to embed more SRAM.

Over 70% of advanced process wafers globally are in TSMC’s hands. The SRAM area of each H100, B200, TPU v5, etc., ultimately becomes TSMC’s revenue.

L1 HBM: The largest profit pool in the AI era

HBM (High Bandwidth Memory) stacks DRAM (Dynamic Random-Access Memory) vertically using TSV (Through-Silicon Via) silicon through-silicon via technology, then packages it via CoWoS next to the GPU as high-bandwidth memory.

HBM almost single-handedly determines how large AI accelerators can run models. SK Hynix, Micron, Samsung hold nearly 100% market share.

As of Q1 2026, the latest market share landscape is: SK Hynix 57–62%, Samsung 22%, Micron 21%. SK Hynix secured a large portion of procurement from companies like NVIDIA and is the current dominant supplier.

Micron’s Q1 2026 earnings call mentioned that the HBM TAM (Total Addressable Market) will grow at about 40% CAGR, from approximately $35 billion in 2025 to $100 billion in 2028, with the milestone reached two years earlier than previous forecasts.

The core advantage of HBM is its extremely high profit margin. In Q1 2026, SK Hynix achieved a record operating margin of 72%.

Reasons for high profits:

1. TSV manufacturing processes sacrifice some traditional DRAM capacity, keeping HBM supply tight.

2. Difficulties in improving advanced packaging yield; Samsung’s share dropped from 40% to 22% partly due to this.

3. Major suppliers are cautious in expanding capacity, and in Q1 2026, they achieved a sequential increase of over 60% in DRAM ASP, indicating a clear seller’s market position.

Among the big three, SK Hynix is driven strongly by HBM, with full-year 2025 operating profit reaching 47.21 trillion KRW, surpassing Samsung Electronics for the first time. In Q1 2026, with a 72% operating margin, it even surpassed TSMC (58.1%) and NVIDIA (65%) in profitability.

Micron has very high growth expectations; Bank of America (BofA) significantly raised its target price to $950 in May 2026. As HBM4 mass production advances, Samsung has the largest potential to regain market share.

L2 Mainboard DRAM

This layer is what we usually call memory modules.

Mainboard DRAM includes DDR5, LPDDR, GDDR, MR-DIMM, and other standard memory products. Currently, it is the highest-selling part of the AI storage system, with the global DRAM market reaching about $121.83 billion in 2025.

Samsung, SK Hynix, and Micron still dominate most of the market. According to the latest data from Q4 2025, Samsung leads with 36.6% market share, SK Hynix is second at 32.9%, and Micron is third at 22.9%.

Currently, capacity is shifting toward higher-margin HBM, maintaining high profitability and pricing power for memory. Although the profit margin of conventional mainboard DRAM products is lower than HBM, its overall market size is the largest.

L3 CXL Pooling Layer

CXL (Compute Express Link) allows DRAM to be pooled from a single server motherboard to the entire rack.

Post-CXL 3.x, all memory within a cabinet can be shared and scheduled among multiple GPUs, allocated on demand. This solves issues like KV cache, vector databases, and RAG indexes that cannot fit or be moved during AI inference.

CXL memory modules will generate only $1.6 billion in 2024, but are projected to reach $23.7 billion by 2033. It appears that the oligopoly of Samsung, SK Hynix, and Micron will persist.

In this layer, Astera Labs produces retimers (re-timers) between CXL and PCIe and smart memory controllers, holding about 55% of this submarket. Its latest quarterly revenue is $308 million, up 93% YoY, with a non-GAAP gross margin of 76.4%, and net profit up 85% YoY. Quite a lucrative segment.

L4 Enterprise SSD: The biggest beneficiary in the inference era

Enterprise NVMe SSDs are the main battlefield for AI training checkpoints, RAG indexes, KV cache offloading, and model weight caching. QLC large-capacity SSDs have already displaced HDDs from AI data lakes.

In 2025, the enterprise SSD market is about $26.1 billion, with a CAGR of 24%, expected to reach $76 billion by 2030.

The landscape remains dominated by the three giants.

Based on Q4 2025 revenue, market shares are: Samsung 36.9%, SK Hynix (including Solidigm) 32.9%, Micron 14.0%, Kioxia 11.7%, SanDisk 4.4%. The top five account for about 90%.

The biggest change at this layer is the explosion of QLC SSDs in AI inference scenarios. SK Hynix’s subsidiary Solidigm and Kioxia have produced 122 TB single-disk capacity products, with KV cache and RAG indexes spilling over from HBM to SSD.

From a profit pool perspective, enterprise SSDs do not achieve HBM’s extreme margins but benefit from capacity-driven and inference expansion double dividends.

Hynix and Kioxia are relatively pure plays. Samsung and SK Hynix enjoy the combined benefits of HBM, DRAM, and NAND, making them more comprehensive AI storage platform companies.

L5 NAS and Cloud Object Storage: The compound interest pool of data attraction

NAS and cloud object storage are the outermost layers for AI data lakes, training data, backups, and cross-team collaboration. In 2025, NAS is about $39.6 billion (CAGR 17%), and cloud object storage about $9.1 billion (CAGR 16%).

Major enterprise storage vendors include NetApp, Dell, HPE, Huawei; SMBs are served by Synology, QNAP. Based on IaaS market share, AWS accounts for about 31–32%, Azure 23–24%, Google Cloud 11–12%, totaling roughly 65–70%.

The profit in this layer mainly comes from long-term hosting, data egress, and ecosystem lock-in.

To summarize,

1. DRAM has the largest market share but the lowest margin at 30–40%; HBM’s market share is only one-third of DRAM but with margins doubling to over 60%; CXL retimers have the smallest market share but the highest margins at over 76%. The closer to compute, the scarcer and more profitable the layer.

2. The main sources of profit growth are threefold: HBM (CAGR 28%), enterprise SSD (CAGR 24%), and CXL pooling (CAGR 37%).

3. Each layer has different business barriers: HBM relies on technological barriers like TSV, CoWoS, and yield improvements; CXL depends on IP and certification, with retimers supplied by a single supply chain; service layers depend on switching costs.