Recently, I had the chance to research Micron Technology in depth. Honestly, I’m surprised by how little presence this company has. Hidden behind Nvidia and TSMC, it receives little attention, yet it supports the very foundation of AI infrastructure.

When I think back, in 2012, when Japan’s Elpida went bankrupt, it was Micron that acquired those assets. At that time, the DRAM memory industry had almost disappeared from Japan, and Samsung and SK hynix of South Korea dominated the market. Among them, only Micron survived in the U.S. as the sole company capable of mass-producing advanced memory chips.

Why is this happening? As AI advances rapidly, everyone is talking only about computation speed—GPU performance, TFLOPS, processing power. But in reality, the bottleneck is somewhere completely different: memory bandwidth.

The time a GPU spends waiting for data after it finishes computing ends up being longer than the actual computation time. This is called the memory wall. To run a model with 70 billion parameters, you need about 140GB of memory in FP16 format. High-end GPU cards like the A100 and H100 have video memory in the range of about 80GB to 192GB. In other words, data has to be split and processed across multiple cards.

To solve this problem, Nvidia introduced high-bandwidth memory right next to the GPU—what’s called HBM. It stacks multiple DRAM die layers vertically and packages them on a silicon interposer. Micron manufactures this HBM.

HBM is not just memory; you could say it is the heart of AI computing. During the inference phase, the GPU’s compute workload is extremely low, and the entire system is completely constrained by memory bandwidth. The energy consumed for data transfer can be 100 to 200 times that of the computations themselves. In other words, much of a data center’s power consumption is used for bus transmission.

The reason Micron isn’t more prominent is that they haven’t pursued flashy architectural innovations. Nvidia innovates in GPU design. TSMC innovates in the logic-chip manufacturing process. Meanwhile, Micron does the unglamorous but essential work: process technology evolution at the 1ガンマノード, complex stacked packaging, and optimization of energy efficiency.

Manufacturing HBM requires stacking multiple layers of DRAM die vertically, and if any one layer has defects, the entire module becomes unusable. The overall yield for 8-layer HBM3E is about 61%. For 12-layer HBM4, it drops to 48%. The impact of each layer accumulates multiplicatively, not additively.

SK hynix accounts for more than 50% of the HBM market because their MR-MUF liquid encapsulation technology directly improves yield for interlayer bonding. Meanwhile, Micron uses the TC-NCF process, which is inferior to hynix in terms of heat dissipation. However, Micron’s HBM consumes 20% to 30% less power, differentiating itself on energy efficiency.

The global DRAM market is dominated by Samsung, SK hynix, and Micron, accounting for 95%. But their positions are completely different. Micron is advancing its process technology at the fastest pace—boosting memory density per wafer and reducing manufacturing cost per bit.

Samsung faces yield bottlenecks at process nodes below 14nm, and its supply pace is slowing. SK hynix’s process evolution speed is roughly on par with Micron.

Micron’s P/E ratio of 21x—far higher than the previous 8–10x typical of traditional memory companies—has risen sharply. The reason is HBM’s made-to-order production model. They sign long-term supply contracts in advance with customers like Nvidia, fixing prices and quantities. It has been reported that Micron’s HBM production capacity for 2026 is already sold out.

This has greatly reduced the cyclical uncertainty typically faced by memory companies. Wall Street has also recognized this, repositioning Micron as an infrastructure provider. In addition, the geopolitical backdrop—where the U.S. needs domestic advanced memory manufacturing—has accelerated capital inflows from institutional investors.

The next battleground for HBM is CXL. CXL is short for Compute Express Link. It is a protocol that shares memory across multiple servers and automatically manages cache coherence. In hyperscale data centers, memory idle rates reach 20% to 30%. This can be addressed with CXL memory pooling.

Micron has announced CXL Type 3 memory expansion modules. HBM enables low latency with extremely high bandwidth measured in hundreds of gigabytes, while CXL modules deliver terabyte-class capacity and flexible memory allocation. By using both together, frequently accessed hot data can be offloaded to local HBM, and cold data can be offloaded to the CXL memory pool.

If you ask what HBM is, the answer is that it’s not just memory—it’s an inevitable product of the evolution of AI infrastructure. As growth in compute capability far outpaces growth in memory bandwidth, the only way to overcome this physical bottleneck is HBM.

In the long run, the semiconductor industry will face limits in materials science. Planar scaling is approaching physical limits, and the yield decline from 3D stacking increases exponentially. In-memory computing also has fundamental process contradictions. DRAM transistors require low drain voltages, while logic chips require low-threshold voltages. These two needs are completely incompatible.

Ultimately, Micron’s competitiveness will depend not on a single technology, but on a comprehensive ability to make fewer mistakes than competitors across multiple areas—improving yields, refining packaging processes, and integrating systems. Building that capability requires decades of manufacturing experience. That is the true moat.