When Will the AI Bubble Burst? From Compute Frenzy to Efficiency Awakening

This article has been compiled and refined based on the speaking materials provided by the author, Wang Tao, on July 18, 2026, at the international seminar “Artificial Intelligence and Environment White Paper” hosted by Fudan University’s China Studies Institute.

Introduction: An era obscured by a computing-power myth

In 2025, when Nvidia released its Blackwell-architecture GPUs, the entire tech industry fell into a near-religious frenzy once again. Peak compute per single card increased by about 2,000 times compared with a decade earlier—this number was recited again and again, as if it were the Tower of Babel that leads AI to Artificial General Intelligence (AGI). Yet behind this dazzling figure, a deeper question was intentionally or inadvertently ignored: of this 2,000-fold improvement, how much is genuine hardware progress? How much is “precision magic”? And how much is merely an industry correction for the era of compute oversupply created by the normal operation of Moore’s Law?

This article will draw on Nvidia data center GPU compute-evolution figures from 2015 to 2025, and combine them with the performance-attribution framework proposed by Professor Bill Dally to deeply examine the real room for AI infrastructure development. We will see that “Huang’s Law”—a concept packaged as the “Moore’s Law of the AI era”—has its four engines, with at least two (or more) already sputtering and about to stall. More importantly, we will reveal a historical truth that the mainstream narrative has long concealed: during the period when Moore’s Law was running normally, the entire computing industry was not pursuing efficiency, but systematically wasting compute. The WINTEL alliance manufactured upgrade demand by lowering hardware utilization efficiency, creating an era in which efficiency was suppressed for a long time.

As the ceiling of compute growth draws ever closer and the countdown to the bursting of the AI bubble begins, we need to reassess: the future of artificial intelligence—what kind of foundation is it actually built on?

Part One: Compute Evolution—The Truth Behind the 2,000-Fold Figure

1.1 The “Magic” of Numbers: The “Precision Game” from FP32 to FP4

First, let’s face the most shocking set of numbers directly: from 2015 to 2025, peak compute per single Nvidia data center GPU increased by about 2,000 times. According to MIT FutureTech research, compute in the same FP16 regime doubles roughly every 1.44 years. This means that if we measure against the traditional transistor-density Moore’s Law doubling period (18–24 months), AI compute’s doubling speed is nearly 6 times faster—this is “Huang’s Law” repeatedly touted by Nvidia CEO Jensen Huang.

However, these numbers don’t hold up under scrutiny. Based on the attribution framework proposed by Professor Bill Dally (Professor of Computer Science at Stanford University and Nvidia’s Chief Scientist), the 2,000-fold improvement can be broken down into the product of four elements:

First: Low-precision numeric representations (contributing about 32×, accounting for 46% of the total improvement). From FP32 (single-precision floating point) to FP16 (half-precision), then to FP8, up to the latest FP4—each halving of bit width achieves an approximate doubling of compute within the same area and power. The Blackwell architecture even introduced native hardware support for FP4/FP6. This is undoubtedly the biggest contributor to AI compute growth over the past decade—but at its core it’s a “precision trade,” not a like-for-like hardware advancement. It’s like changing a ruler from millimeter markings to centimeter markings: readings become 10 times faster, but measurement precision drops by 10 times as well.

Second: Tensor cores and complex instructions (contributing about 12.5×, accounting for 33%). From FMA (fused multiply-add) to HMMA (half-precision matrix multiply-add), to IMMA (integer matrix multiply-add), and up to Hopper’s Transformer Engine— the amount of computation performed per instruction grows exponentially. The path began when the Volta architecture introduced Tensor Core in 2017, and by Blackwell in 2025 it contributed more than one-third of performance improvement. But this is architectural optimization, not an increase in underlying transistor density.

Third: Process technology and advanced packaging (contributing about 2.5×, accounting for 12%). From 28nm to 16nm, 12nm, 7nm, and then to 4N/4NP processes, the process benefits of traditional Moore’s Law contributed only about 2.5× improvement over this decade. More importantly, to maintain this share, the Blackwell architecture had to adopt a dual-die stitching approach (NV-HBI) and dramatically raise power from 250W to 1,400W. This means the contribution from pure process shrink is already extremely limited, and the industry is forced to rely on “more parts” and “more power” to sustain growth.

Fourth: Structured sparsity (contributing about 2×, accounting for 9%). Since the Ampere architecture starting in 2020, Nvidia has supported 2:4 sparsity—pruning 2 weights out of every 4, enabling a direct 2× throughput increase. But this is essentially “cheating”: it assumes models can tolerate 50% weight sparsity without significantly losing accuracy, and that assumption does not hold for all workloads.

Multiplying these four factors: 32 × 12.5 × 2.5 × 2 ≈ 2,000. This is the entire secret behind those dazzling numbers. Of the improvement, more than 79% (46%+33%) comes from “tricks” at the precision and architecture levels, not from hardware progress in the traditional sense. If we exclude low-precision representations and tensor cores and only look at improvements driven by process and sparsity, then the actual hardware progress over the decade is only about 5× (2.5×2).

1.2 Huang’s Law’s “Four Engines” and the Sputtering Crisis

Jensen Huang describes the growth of AI compute as “Huang’s Law,” claiming that the doubling cycle of full-stack compute throughput equivalent to FP16 is only 6 months—6 times faster than the traditional Moore’s Law. Yet this “law” is now facing unprecedented challenges.

Let’s carefully examine the “four engines” of Huang’s Law:

Engine One: Low-precision numeric representation. The path from FP32 to FP16, then FP8 and FP4, has already reached its end. FP4 means each value is represented with only 4 bits, allowing it to express just 16 distinct values. Further compressing to FP2 (2 bits, only 4 values) is infeasible in most AI scenarios, because quantization error would cause model accuracy to collapse. In fact, the industry has already encountered significant accuracy loss at FP4, requiring complicated quantization-aware training and dynamic range scaling to barely make it usable. This engine is already on the verge of stalling.

Engine Two: Tensor cores and complex instructions. From FMA to HMMA and IMMA, to Transformer Engine, instruction complexity is approaching the physical limit. Transformer Engine is essentially a hardware accelerator customized for the Transformer architecture, but AI model architectures are evolving rapidly—new architectures such as Mamba, RWKV, and RetNet increase the risk of “architecture lock-in” for hardware optimized for a specific architecture. In addition, the amount of computation performed per instruction cannot grow infinitely—it is constrained by physical limits such as memory bandwidth and on-chip cache. This engine, too, is slowing down significantly.

Engine Three: Process technology and advanced packaging. This is the core engine of traditional Moore’s Law, and it is currently also the weakest engine. Processes below 3nm face multiple challenges including quantum tunneling effects, a surge in leakage current, and photolithography technical limits. TSMC’s 2nm process, N2, is scheduled for mass production by the end of 2025 (the mass production timeline for 3nm N3 started at the end of 2022, taking exactly 3 years). At present, it is in the capacity ramp-up stage and is the first globally to achieve scaled production of GAA chips. But transistor-density gains are no longer nonlinear. More severely, the cost of advanced process technology rises exponentially. According to IBS data, the cost of a 3nm wafer already exceeds $20k, while 2nm is expected to exceed $30k. “Economic Moore’s Law”—the continuous decline in cost per transistor—permanently disappeared in 2020. Nvidia’s dual-die stitching in Blackwell and its 1,400W power draw are a helpless response after process benefits have dried up.

Engine Four: Structured sparsity. 2:4 sparsity is already a relatively aggressive pruning ratio. Extending it further to 1:4 or even more extreme sparsity patterns will severely impact model accuracy. Moreover, the performance gains from sparsity depend on specific hardware support and software-stack optimization, limiting generality. This engine has never truly operated at full speed.

Among the four engines, the two most core drivers—low-precision representation and process shrink—have clearly either stalled or are slowing down. Tensor cores and sparsity are still operating, but the trend of diminishing marginal returns is irreversible. That’s why, even though Nvidia’s single-card native FP16 tensor compute maintained a 1.4–1.8 year doubling cycle in the first 7 years (2015–2022), it has slowed to 3.5–4 years in the past 3 years (2022–2025). The “6-month doubling” of Huang’s Law has already become history.

1.3 Comparison with Traditional Moore’s Law: The End of an Era

Let’s place the growth of AI compute within a more macro historical frame.

Traditional transistor-density Moore’s Law did maintain an 18–24 month doubling cycle in the early years (1970s–2000s). But over the past 10 years, this cycle has stretched to about 3 years. According to industry consensus, the doubling cycle will further extend to 3.5–4 years before 2032; 2032–2038 will be 5–6 years; after 2038, silicon-based planar shrinking will fail completely, and the doubling cycle could be as long as 8–10 years.

Huang’s Law of AI compute—while in the first decade (2015–2025) it achieved growth that appeared to surpass Moore’s Law through “precision trade-offs” and architectural innovation—its underlying driving force is quickly running out. Over the next 5 years, performance improvements in Nvidia chips will enter a plateau period, and the speed of Huang’s Law will rapidly stretch from a 6-month doubling cycle to 1 year, 2 years, 4 years, or even 8 years. This is not alarmism; it is an inevitable inference based on physical constraints and economic laws.

Even more noteworthy: since 2020, the “economic Moore’s Law,” in which costs decline in parallel, has permanently disappeared. This means that even if transistor density continues to grow slowly, the cost—and even the power consumption—per unit of compute no longer decreases, and may even rise. For the AI industry that relies on scaling up compute, this is a fatal signal.

Part Two: The Hidden History—Efficiency Suppression in the Moore’s Law Era

2.1 The WINTEL Alliance’s “Artificially Lowered Efficiency”

Before diving into the future of AI compute, we must first clarify a historical truth that mainstream narratives have long concealed: during the era when Moore’s Law was running normally, the entire computing industry was not pursuing efficiency—it was systematically suppressing and reducing efficiency.

The late 1980s to the early 2000s were the golden age of Moore’s Law. CPU performance doubled every 18 months, and the number of transistors grew exponentially. Yet this growth did not bring a corresponding efficiency improvement. Instead, the industry’s dominant logic was: since compute growth is so fast, why bother optimizing software efficiency?

A widely circulated joke is that people in the industry even called for CPUs not to grow so quickly—“486 is enough.” This is not a joke. In the Windows 95 era, a PC equipped with a 486 processor was already sufficient to run most of the applications of that time. If software efficiency stayed constant, users would have no incentive to upgrade hardware. And hardware vendors—especially the WINTEL alliance formed by Intel and Microsoft—built their business model precisely on continuous upgrades.

Thus, a strange industrial ecosystem emerged: hardware vendors did everything they could to increase transistor density, while software vendors did everything they could to “consume” the additional compute. Each new generation of Windows made the operating system bulkier than the previous one, and Office stacked features far beyond actual needs; web browsers’ memory usage grew exponentially. This is not technological progress—it is a carefully designed form of “planned obsolescence” manufactured by lowering software efficiency to create demand for hardware upgrades.

2.2 The Absurdity of a Linux+Windows Emulation Platform Being 10× Faster than Native Windows

The clearest evidence for this comes from a test case repeatedly referenced within computer science.

Someone designed an experiment: run a Windows emulation platform on Linux (such as Wine or a virtual machine), and then run Windows applications on that emulation platform. Intuitively, running the native Windows applications directly on Windows should be smoother than this “layered house of cards,” since every additional abstraction layer adds overhead.

However, the test results were astonishing: software running on the Linux+Windows emulation platform was nearly 10 times faster than running it directly on Windows.

This seemingly absurd result actually reveals, in depth, the WINTEL alliance’s efficiency suppression mechanism. The Windows operating system’s design itself includes a large amount of redundant code preserved for compatibility with older hardware and older software, as well as sacrificing optimization headroom to maintain backward compatibility. More importantly, Windows’s underlying architectural decisions—such as memory management, process scheduling, and system call interfaces—were largely made to adapt to Intel’s hardware characteristics, not to pursue maximum efficiency. Intel’s CPU designs were also shaped by the historical baggage of maintaining compatibility with the x86 instruction set, retaining many complex instructions and microarchitecture designs that have long been obsolete in modern computing.

This “hardware-software conspiracy” produces a lock-in state of low efficiency. Because Linux has no such historical baggage, its kernel design is more streamlined and efficient. When running the Windows emulation platform on Linux, it effectively strips away much of the redundant overhead present in the Windows native environment. That’s why, despite adding an extra abstraction layer, real performance improves by nearly 10×.

This test case happened in the early 2000s, but the structural issues it reveals run throughout the entire Moore’s Law era. In an environment of compute oversupply, efficiency optimization was not rewarded—it was regarded as “unnecessary work.”

Storage structures were also highly irrational and artificially engineered to create massive inefficiency. Years ago, I was the Chief Engineer at Wangma Computer (Huizhou). While developing database software, I conducted a test: using a disk emulator on the then-DOS platform, I virtually created a disk in memory. Then I loaded all database software and data entirely into this in-memory virtual disk. Just that simple change boosted the runtime efficiency by 10 to 20 times! Later, I conducted many more experiments and published the results in a research article titled “Massive Memory Computer” in 1998 in the “Computer World” newspaper. A decade later, SAP proposed “in-memory computing.” The principle was completely identical to my “massive memory computing.”

2.3 The “Late Arrival” of Multi-Core Technology: A Forgetting of Amdahl’s Law

Another efficiency dimension long ignored is parallel computing.

Efficiency calculations for large-scale parallel processing were precisely described as early as 1967 in Gene Amdahl’s “Amdahl’s Law” form: no matter how many processors you add, the speedup of a program is limited by the proportion of the serial portion. If 10% of a program’s code must execute serially, then even with infinitely increasing the number of processors, the maximum speedup tops out at 10×. In between, a compromise exists: increasing the number of processors can effectively improve overall performance.

Yet Intel’s attitude toward multi-core technology can only be described as “dull.” Although Amdahl’s Law had been widely known in academia for a long time, and multi-core architectures had already matured in servers and high-performance computing, Intel did not release its first dual-core CPU aimed at the consumer market (Pentium D) until 2005. Mainstream dual-core processors (Core Duo) did not roll out at scale until 2006.

Why? Because in an era when single-core performance was still steadily growing according to Moore’s Law, promoting multi-core meant acknowledging that single-core performance growth was about to hit a ceiling. It also implied the need for a fundamental software ecosystem redesign—complexity in multi-threaded programming far exceeds that of single-threaded programming. It also potentially weakened Intel’s monopoly advantage in single-core performance. Instead of taking the risk to push a multi-core revolution, it was safer to move slowly within the comfort zone of improving single-core performance.

This strategic delay wasted at least a decade of the industry’s time on parallel-compute efficiency. Only after 2005, when single-core performance growth visibly slowed, was Intel forced to pivot toward multi-core. By then, the software ecosystem’s parallelization overhaul was already badly lagging—many applications still can’t fully utilize the potential of multi-core CPUs to this day.

2.4 The Systemic Consequences of Efficiency Suppression

Looking back at the era when Moore’s Law was active, we can clearly see a main line of “efficiency suppression”:

• Chip layer: The complexity and historical baggage of the x86 instruction set leads to a large number of transistors being used for decoding and compatibility rather than actual computation. In Intel’s CPU design, the share of circuits maintaining backward compatibility has long remained high.

• Hardware system layer: The “Memory Wall” problem was proposed as early as the 1990s, but only in the past decade have technologies such as high-bandwidth memory (HBM) and near-memory computing begun to receive serious attention. In an era of compute oversupply, memory bandwidth bottlenecks were simply addressed by “waiting.” As a result, in prior computing systems, in fact more than 95% of the time the CPU was waiting for data storage. This is exactly why my proposed “massive memory computing” can greatly improve efficiency.

• Software layer: There is insufficient motivation to optimize operating systems, compilers, and application software. “Hardware will solve this problem” became a catchphrase for software engineers. The widespread adoption of high-level languages such as Java and Python improves development efficiency, but at the cost of runtime efficiency.

• System layer: Resource waste in distributed computing and cloud computing is striking. Many data center servers have long operated at utilization rates below 20%, but due to lack of economic incentives, there is insufficient drive to optimize.

This systematic efficiency suppression was concealed during the era when Moore’s Law was in effect—after all, compute doubled every 18 months, so who cared about efficiency? But precisely this concealment planted the seeds for today’s predicament and the space for improvements like Huang’s Law: when Moore’s Law approaches total failure, we discover that the hardware efficiency of the past was actually that bad. Huang’s Law is not about how fast Nvidia can improve—it’s about how brutally efficiency was suppressed in the era when Moore’s Law dominated.

Part Three: Awakening to Efficiency—Catching Up from 2010 to Today

3.1 Moore’s Law Slows: Forced Start of Efficiency Optimization

2010 was a turning point.

That year, Intel’s 32nm process began mass production, but transistor-density growth had already clearly slowed. More importantly, CPU clock frequencies hit a “power wall” around 2004 and then stagnated for nearly 6 years. Moore’s Law’s “free lunch”—automatic performance gains from process progress—officially ended.

The industry was forced to start “catching up”: since physical growth of hardware is constrained, effort must be spent on efficiency.

Efficiency improvement work in this period can roughly be divided into several layers:

Process layer: FinFET (fin field-effect transistors) was introduced in 2011. By improving gate control through a three-dimensional structure, it delayed short-channel effects. GAA (gate-all-around) transistors began ramping into mass production after 2022, further improving gate control. But these are technologies that “extend Moore’s Law,” not a breakthrough new paradigm.

Architecture layer: Multi-core became mainstream, and heterogeneous computing (CPU+GPU) began to spread. ARM architectures rose in mobile due to their low-power advantage, which in turn drove the x86 camp to reflect. The emergence of open-source instruction sets such as RISC-V broke the monopoly of x86 and ARM, opening new paths for customized, high-efficiency chip design.

Software layer: Compiler optimizations, parallel programming frameworks (such as CUDA and OpenCL), and advances in memory-management technologies began to make up for historical shortfalls. Containerization (Docker), microservices architectures, and Serverless computing essentially improve system-level efficiency through finer-grained resource scheduling.

Algorithm layer: In deep learning, algorithm efficiency improvements were especially significant. From AlexNet (2012) to ResNet (2015), and then to Transformer (2017), the evolution of model architectures not only improved accuracy but also, to some extent, optimized compute efficiency. But the truly revolutionary algorithmic efficiency shift would only fully erupt in the 2020s.

Even the liquid-cooling techniques used in the early days of integrated circuit development are being brought back today.

Large memory has become one of the main methods to address CPU waiting.

......

3.2 Huawei’s “He Tingbo’s Law”: China’s Efficiency Philosophy

In the wave of awakening to efficiency, the contributions of Chinese enterprises cannot be ignored. The “He Tingbo’s Law” proposed by He Tingbo, President of Huawei HiSilicon, though not as universal as Moore’s Law or Huang’s Law, shares a core idea: under process constraints, maintain performance growth through architectural innovation and system optimization. This represents the correct direction for the post-Moore’s Law era.

Huawei, facing the extreme environment of U.S. sanctions and restricted access to advanced processes, achieved performance approaching international advanced levels even on 7nm and 14nm processes through deep redesign of chip architectures, deep system-level optimization, and extreme co-optimization of software and hardware—by using logic folding to continuously reduce signal-transmission time delay. This “trade efficiency for performance” approach sharply contrasts with the WINTEL-era logic of “trade hardware for performance.”

The essence of He Tingbo’s Law is: when process dividends dry up, architectural innovation, system optimization, and ecosystem coordination become the primary sources of performance growth at the hardware level. This law applies not only to Huawei, but to the semiconductor industry across the entire post-Moore’s Law era.

3.3 Bottlenecks in Efficiency Gains: Diminishing Marginal Returns

However, we must remain clear-headed: all efficiency-improvement efforts have physical limits and patterns of diminishing marginal returns.

From 2010 to now, efficiency improvement work has already been going on for nearly 15 years. On the process side, FinFET to GAA evolution has nearly approached the physical limits of silicon-based materials. Once the practical feature width was reduced to 22nm, it has effectively been impossible to keep shrinking. Today, the so-called “5nm,” “3nm,” and “2nm” are not truly line widths anymore, but equivalent line widths. At TSMC’s 2nm, the actual physical gate length Lg (the switch channel width) of GAA transistors is about 10–12nm. It has become extremely difficult to further shrink transistor sizes.

On the architecture side, technologies such as multi-core, heterogeneous computing, and near-memory computing have been widely deployed, but the memory wall and power wall problems have not fundamentally been solved;

On the software side, the room for compiler optimization is shrinking, and the complexity of parallel programming limits the full release of multi-core potential;

More importantly, the “low-hanging fruit” for efficiency improvements has already been picked. The remaining optimization space either requires disruptive technological breakthroughs (such as quantum computing, optical computing, neuromorphic computing) or requires systemic restructuring of the industrial ecosystem (such as entirely new programming models, memory hierarchies, and interconnect architectures). None of these can be achieved within 5–10 years.

Therefore, an unavoidable conclusion is: over the next 5 to 10 years, efficiency-improvement efforts will inevitably encounter bottlenecks and limits, trending toward stability. Huang’s Law, like Moore’s Law, will enter a plateau period. He Tingbo’s Law will be similar.

Part Four: DeepSeek Path and Knowledge Compression—Rescue at the Algorithm Level

4.1 DeepSeek R1 and V4: A Revolution in Algorithmic Efficiency

Against the backdrop of hardware growth hitting its peak, algorithm-level efficiency improvements have become one of the best routes for the AI industry to “self-rescue.” DeepSeek’s rise is the best footnote to this logic: since compute growth is becoming harder, find ways to achieve with less compute.

On January 20, 2025, DeepSeek released the R1 model. Compared with OpenAI’s O1 model, R1 requires only 1/10 to 1/20 of the compute for the same task quality, and its cost is only 1/27. This number shocked the industry—meaning that through algorithmic innovation, you can achieve order-of-magnitude performance improvement without increasing hardware investment.

On April 24, 2026, DeepSeek released the V4 model. Compared with R1, for the same workload V4 reduces compute requirements by another 1/3. This means that in less than a year and a half, through algorithm optimization, DeepSeek compressed the compute needs for the same tasks to about 1/30 to 1/60 of O1. The cost is less than 1% of O1.

DeepSeek’s success is not accidental. It represents the comprehensive rise of the second growth curve in AI—“algorithmic efficiency.” When growth in hardware compute slows down, improvements in algorithmic efficiency become key to sustaining AI capability growth. This is similar to the historical shift in the automobile industry after the oil crisis—from “large displacement” to “high efficiency.”

4.2 Redundancy of Knowledge and Information: The Compression Space That’s Been Ignored

However, improvements in algorithmic efficiency also have their limits. Therefore, compressing knowledge and information at the very source becomes the ultimate method. Human-created knowledge and acquired information contain larger redundancy. To understand this, we need to delve into the redundancy problem in human knowledge and information.

According to a famous study published in The Lancet in 2009 (Chalmers & Glasziou), about 85% of global research investment is wasted. The sources of waste include: duplicate research, low-value research topics, research that isn’t published or published incompletely, and reports that are unavailable. This means that within the global research investment of hundreds of billions of USD per year, only about 15% truly produces valuable increments in knowledge.

This redundancy is evident across multiple levels:

Literature layer: The same scientific conclusion is often restated hundreds or even thousands of times in different papers. Each new paper makes small modifications or expansions on prior work, but the core contribution may already have been fully articulated. A textbook is essentially a high-level de-duplication of tens of thousands—even hundreds of thousands—of original papers. It compresses scattered effective information into a coherent knowledge system.

Network information layer: The duplicate rate of web content is commonly estimated at 30%-50%. Mirrored websites, reposted content, “article washing” (spun/copied content), and SEO-driven low-quality content form a huge redundancy in internet information. Search engines alleviate this problem somewhat through indexing and ranking mechanisms, but they do not fundamentally remove redundancy.

Language expression layer: The redundancy in human language is about 50%-75%. This means that in typical text, about half to three-quarters of characters or words are not strictly necessary for conveying core information. Language redundancy is reasonable—it provides fault tolerance, emotional expression, and cultural context—but from an information theory perspective, it does represent massive redundancy of knowledge and information, and potential compression space.

Based on the “unified measurement” framework I established: since after the modern scientific revolution began, only mathematics had unified terminology systems, while experiments and measurement did not, this leads to enormous knowledge redundancy across different human disciplinary fields.

Combining these three layers, the overall order of magnitude of redundancy in human knowledge and information itself is estimated to be between 1,000 and 10,000 times. This means that if we can build a highly de-redundant knowledge representation system, the amount of knowledge that the same storage capacity can hold would be 1,000 to 10,000 times more than today.

4.3 Large Language Models: A Massive Information Compressor

Interestingly, large language models (LLMs) themselves are a massive information compressor. We can understand their compression ability in three ways:

Byte-level compression: the ratio of the total volume of training corpus to the volume of model weights is about 80:1. This means that a trained LLM compresses tens of billions to hundreds of billions of bytes of training data into tens of billions of bytes’ worth of weight parameters.

Memory-level compression: considering the actual amount of information stored per parameter (about 3.6 bits), the ratio of information actually stored in the corpus vs in the model is about 200:1. This further accounts for the impact of parameter precision (such as FP16, FP8) on information capacity.

Knowledge-level compression: the ratio of effective knowledge after redundancy removal to model memory capacity is about 15–25:1. This is the strictest metric; it assumes the model not only stores information, but also understands the relationships among information, forming a transferable knowledge representation.

For example, take “pig.” In English, there are dozens of commonly used words related to “pig”: pig (most common), swine (formal/collective noun), hog (large pig), porcine (adjective), Suidae (pig family), piggy/piglet (nickname for small pigs), boar (male pig/wild boar), sow (female pig), gilt (young sow), shoat (recently weaned piglet), barrow (castrated male pig)…… plus words related to parts and products (pork, bacon, ham, sausage, lard, trotters, etc.), for a total of more than 30 words pointing to the same core concept. This kind of over-division of concepts is a typical manifestation of knowledge redundancy.

4.4 “Civilization Studies”: An Ambition to Rebuild Human Knowledge Systems

Facing an ocean of knowledge redundancy, the work we are trying to do is to create an academic platform called “Civilization Studies,” to systematically rebuild the entire human knowledge system.

The core idea of “Civilization Studies” is: reorganize and express all human civilization knowledge using the smallest possible, de-redundant concept体系. It is similar to the axiomatization method in mathematics—starting from the minimal set of axioms to derive the entire theoretical system. Within the framework of “Civilization Studies,” each knowledge point is theoretically precisely placed in its unique position in the logical network, eliminating repeated expressions and conceptual confusion.

Large language models have already demonstrated the astonishing ability to compress knowledge. If we can further convert LLMs’ “implicit knowledge” into “explicit structures,” and build a standardized, machine-readable knowledge representation language, then the organization and dissemination efficiency of human knowledge will increase by orders of magnitude.

Civilization Studies is a must for the future development of AI, and it is also the required response for humans to the challenges posed by AI. It not only improves AI, but also enables humans to possess the kind of all-round knowledge learning and application capabilities that match the AI era.

Part Five: AI Intelligence Levels—Overestimated and Underestimated

5.1 The Lesson of “Two Days, Five Papers, Tens of Thousands of Words”

Today’s progress in AI intelligence is indeed astonishing. Recently, I used a test version of KiMi K3 and, within two days, generated 5 high-level papers of tens of thousands of words each. Including abstracts, keywords, introductory literature review, charts, references, and citation markers in the main text—all of this was generated automatically and formatted very consistently.

This capability is truly impressive. It indicates that in the dimensions of “formal structure compliance” and “information integration,” AI has reached—indeed, surpassed—most human researchers. Of course, the quality of rapidly generated papers highly depends on the quality of the input instructions. It’s like a computer platform: you input the software instructions, and it produces the corresponding result.

5.2 The Overestimated “Singularity” and the Underestimated “Platform”

In recent years, the U.S. tech community has been talking a lot about “Technological Singularity” and “Artificial General Intelligence (AGI),” with the implicit assumption that as long as compute keeps increasing, AI intelligence will exponentially improve, eventually surpassing humans and causing a civilizational qualitative transformation.

However, based on the analysis of hardware growth and algorithmic efficiency earlier, the foundation of this assumption is shaking: the compute of AI chips and the overall system compute will quickly enter a plateau, not cross over a singularity. Without continuous exponential growth of underlying hardware, the compute premise of “singularity” no longer exists. This isn’t pessimistic prediction—it’s respect for physical limits and economic laws. During a plateau period, AI capabilities may still grow slowly, but not exponentially in a burst. This means that the timeline for achieving AGI (if it truly exists) needs to be pushed back significantly—from “2027” or “2030” predicted by some optimists to an “uncertain future.”

Part Six: The Inevitable Bursting of the AI Bubble

6.1 What the Bubble Consists Of: The Divergence Between Capital, Narratives, and Reality

When hardware growth enters a plateau period, marginal returns in algorithmic efficiency diminish, and capital markets’ expectations still cling to the narrative of “exponential growth” and “singularity arriving,” the bursting of the bubble becomes inevitable.

The current AI industry bubble mainly shows up in the following aspects:

Valuation bubble: The market capitalizations of AI-related companies are largely built on the narrative that “compute is power.” Nvidia’s P/E ratio has remained high for a long time, reflecting market expectations of its continuous ultra-fast growth. But once it becomes clear that hardware growth is slowing, valuation corrections will be severe.

Investment bubble: Global venture capital in AI reached an unprecedented scale between 2023 and 2025. Large amounts of capital flooded into foundation model training, AI chip design, and various AI application startups. However, many investments rely on the premise that “the cost of compute will keep declining,” and that premise is failing.

Application bubble: In consumer markets, AI application retention rates and paid conversion rates are far below expectations. Many products packaged as “AI-native” derive their core value not from AI technology, but from traditional product design and operational capabilities. In the enterprise segment, real deployment also faces practical obstacles such as data quality, integration costs, and compliance risks.

Narrative bubble: Narratives like “AGI is coming,” “AI will replace all white-collar jobs,” and “compute is the oil of the new era” are repeatedly reinforced across media and social networks. While these narratives may be somewhat inspiring, their excessive simplification and their disregard for technical limits are creating dangerous expectation gaps.

6.2 Triggers and Paths to the Bubble Bursting

The bursting of the AI bubble may be triggered by one or more of the following:

Hardware growth falls short of expectations: If the performance improvement of Nvidia’s next-generation architectures (such as Rubin) is significantly lower than market expectations, or if process progress encounters insurmountable physical barriers, market confidence in AI compute growth will collapse rapidly.

Algorithmic efficiency hits a bottleneck: If subsequent models from companies like DeepSeek can no longer continue to maintain the order-of-magnitude reduction in compute demand, the market will realize that “algorithmic efficiency” also has its limits, prompting a re-evaluation of the AI industry’s cost structure.

Macroeconomic headwinds: If the global economy enters a recession cycle, corporate and consumer willingness to invest in AI will drop sharply. AI as a “nice-to-have” technology is often the first target for budget cuts during downturns.

Regulatory tightening: As AI’s social impact becomes increasingly visible, governments across countries are tightening AI regulation. If regulatory measures significantly increase the costs of AI development and deployment, they will accelerate the bubble bursting.

The path of the bubble bursting may resemble the 2000 dot-com bubble: in the short term, valuations sharply correct, many startups go bankrupt, and investment enthusiasm cools quickly. But unlike the dot-com bubble, the AI bubble bursting may lead to a slower industry recovery—because after the dot-com bubble burst, excess fiber and broadband infrastructure provided a foundation for the subsequent Web 2.0 revolution, whereas after the AI bubble bursts, excess compute infrastructure does not necessarily translate into a new wave of application explosions (since the cost of compute no longer declines).

6.3 The Post-Bubble Era: Returning to Mainstream Business Rationality and Value

Although the bubble bursting is painful, it is not necessarily bad. It will force the AI industry to shift from “narrative-driven” to “value-driven,” and from “scale races” to “efficiency races.”

In the post-bubble era, the following trends will become dominant:

Rise of smaller models: When compute is no longer cheap, parameter scale is no longer the only competitive dimension. Smaller task-optimized models with tens of billions of parameters will be more commercially valuable than general models with trillions of parameters.

Edge computing becomes mainstream: Pushing AI inference from the cloud to edge devices can not only reduce latency and protect privacy, but also significantly reduce compute costs. This requires model compactness and highly efficient hardware.

Deep focus on vertical applications: The market for general AI assistants will trend toward saturation, while deep applications in vertical domains such as healthcare, law, finance, and manufacturing will become the main source of value creation. The success of these applications depends on deep integration of domain knowledge, not just piling up compute.

Open-source ecosystems thrive: When commercial investment enthusiasm cools, open-source communities will become the main drivers of AI technological progress. Similar to how Linux rose after the dot-com bubble, open-source AI models and tools will play a key role in the post-bubble era.

Part Seven: Conclusion—Re-examining the Future of AI at the Edge of the Platform

7.1 Recap of the Core Conclusions

Let’s return to the starting point of this article and summarize several key conclusions:

First, about compute growth: from 2015 to 2025, Nvidia’s single-card peak compute increased by about 2,000×, but most (or all) of the four engines behind Huang’s Law are about to stall. Over the next 5 years, compute growth will enter a plateau period.

Second, about historical lessons: in the era when Moore’s Law was active, the WINTEL alliance created upgrade demand by systematically lowering the efficiency of both software and hardware. After 2010, the entire industry was forced to “catch up” on efficiency, but this catch-up will hit bottlenecks within 5–10 years.

Third, about pathways to reduce compute: companies like DeepSeek achieve order-of-magnitude efficiency gains through algorithmic innovation. But the space for this path is also limited, and marginal returns likewise diminish.

Fourth, about AI intelligence: AI has reached a high level in formal compliance and information integration, but there remains a significant gap in core abilities such as originality research, causal reasoning, and common-sense acquisition. The narratives of “singularity” and “AGI” lack the support of continuous exponential growth in underlying hardware.

Fifth, about bubbles and the future: as hardware enters a plateau period and algorithmic efficiency reaches bottlenecks, while capital markets’ expectations still cling to narratives of exponential growth, the bursting of the AI bubble will become inevitable. In the post-bubble era, the AI industry will return to efficiency and value. Smaller models, edge computing, vertical applications, and open-source ecosystems will become dominant.

Sixth, knowledge and information compression centered on Civilization Studies is key for long-term improvement.

7.2 Implications for policymakers and investors

For policymakers, it is necessary to recognize that AI industry competitiveness no longer depends solely on compute scale, but on algorithmic efficiency, data quality, and application deployment capability. Continued large-scale investment in building intelligent computing centers while ignoring algorithmic innovation and ecosystem cultivation will cause huge resource waste. At the same time, efforts should support the construction of long-term knowledge infrastructure such as “Civilization Studies,” laying foundations for knowledge growth in the post-hardware era.

For investors, expectations need to be adjusted: the era of supernormal returns in AI may already be over. Future investment opportunities will be more likely to appear in algorithmic efficiency tools, vertical industry applications, and areas where AI deeply integrates with traditional industries—not in a “military equipment race” of foundation models and compute infrastructure.

7.3 Implications for technical practitioners

For technical practitioners, this is an era of “returning to engineering fundamentals.” When compute is no longer free, every FLOP must be carefully accounted for. Model compression, inference optimization, hardware-software co-design, and deep integration of domain knowledge will become core technical competitiveness. Meanwhile, a cross-disciplinary knowledge structure—knowing both AI algorithms and domain knowledge and systems optimization—will be more valuable than simply “tuning big models.”

7.4 Written at the end: See the real future at the edge of the platform

We are standing at the edge of an era. Over the past decade, the AI industry enjoyed the dividend of exponential compute growth, creating dazzling growth myths. When Huang’s Law’s four engines sputter one by one, when the “catch-up” for Moore’s Law enters a bottleneck, and when marginal returns of algorithmic efficiency diminish, we are forced to face a future that is less glamorous (less dazzling, but also more real): AI is not a rocket toward a singularity; it is an increasingly precise tool in humanity’s toolbox. Its value is not in replacing humans, but in augmenting humans; not in pursuing infinite growth, but in creating the greatest value within finite resources.

At the edge of the platform, we may be able to let go of the obsession with “exponential growth” and re-examine the essence of technology: technology is not the goal, but the means; compute is not power, but a resource; AI is not a god, but a mirror—it reflects human wisdom and also reflects human limitations.

In the next 5 years, the AI industry will experience painful adjustments. After those adjustments, we will enter a more mature, more pragmatic, and more sustainable AI era. That era may not have the splendor of a “singularity,” but it will have the steadiness of “efficiency”; it may not have the fantasy of “general intelligence,” but it will have deep cultivation of “specialized intelligence”; it may not have the arrogance of “compute is everything,” but it will have the humility of “knowledge is power.” There won’t be rigid academic silos separated like castles separated by mountains, but there will be a brilliant future in which “Civilization Studies” creates knowledge across domains.

This is the true space for AI infrastructure development—and also where the future of AI lies.