TSMC's CoWoS capacity is fully loaded, how does the new CoPoS packaging technology increase AI chip production and what are the differences?

TSMC’s CoWoS advanced packaging has become the narrowest bottleneck in the AI supply chain: lead times of 52 to 78 weeks, capacity utilization approaching 98%, and all major orders stalled. A potential solution is the next-generation packaging technology CoPoS.

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• CoWoS Hits a Ceiling
• The Square Breakthrough
• Future Potential and Variables

TSMC’s advanced packaging technology CoWoS, which holds over 60% market share, is stuck on a physical shape issue that cannot be avoided. The reticle area of NVIDIA’s new Rubin GPU is 5.5 times the current specification, allowing at most seven sets to be cut from a single 12-inch circular wafer, and often only four sets due to practical yield considerations.

TSMC’s answer is not to make the circular wafer larger, but to switch to a square shape. This shift could be a race that determines the speed of AI computing supply over the next five years.

CoWoS Hits a Ceiling

CoWoS (Chip on Wafer on Substrate) is TSMC’s most profitable advanced packaging technology. In simple terms, it attaches computing chips and memory chips to a circular interposer, then packages them into a complete AI chip.

The interposer acts as a high-precision adapter board, responsible for high-speed communication between chips. It is made of silicon, and its reticle size is physically limited, making it difficult to enlarge further.

The problem is that wafers are round, but reticles (the maximum area that can be handled in one exposure of the chip) are getting larger. The circular edges leave large areas where complete chips cannot be cut. The larger the chip, the higher the waste ratio. If next-generation GPUs continue with the current architecture, the number of good dies from a single circular wafer will drop to single digits.

High-power AI chips generate a lot of heat during prolonged operation. The thermal expansion coefficients of the chip, interposer, and substrate are different. When cooling, the contraction rates are inconsistent, leading to warpage issues that directly reduce packaging yields.

These limitations combined make CoWoS the narrowest bottleneck in the entire AI supply chain: lead times are 52 to 78 weeks, more than three times the 12 to 18 weeks for logic wafers; capacity utilization remains at 95% to 98%, with a supply-demand gap of about 20%.

Orders from NVIDIA, Google, and Amazon are all fully booked. Even if CoWoS monthly capacity is raised to 140,000 wafers by the end of 2026, it still cannot keep up with demand.

The Square Breakthrough

TSMC’s solution is CoPoS (Chip on Panel on Substrate). Simply put, it replaces the circular wafer carrier for the interposer with a rectangular panel, initially focusing on a 310mm x 310mm substrate.

The key is area utilization efficiency. With the same material, a flagship AI chip can only yield four sets from a circular wafer. With a square panel, conservative estimates suggest 9 to 16 sets. On the same panel area, the output is directly doubled to quadrupled, effectively doubling packaging capacity without adding new equipment.

But this is not simply cutting a circle into a square. The four corners of a square panel are prone to stress concentration during processing, plus uneven thermal expansion. A slight mishap can deform the substrate, potentially lowering yields instead of raising them. TSMC is betting that long-term benefits will outweigh the short-term process adjustment costs.

Future Potential and Variables

The long-term goal of CoPoS is to replace silicon interposers with glass substrates.

Glass is a key turning point because it offers things silicon cannot: it is flatter, larger, bypasses the physical ceiling of silicon wafer reticle size, has lower signal loss, and can stack more memory layers and accommodate larger computing chips. TSMC’s roadmap shows that by 2029, the reticle factor will reach 14x, computing power will increase 48x, and a single package can accommodate 24 HBM5E.

But the advantages and risks of glass are two sides of the same coin. It is hard, brittle, and sensitive to thermal shock. Large-area processing that cracks renders the entire panel scrap, with yield risks far higher than mature silicon processes. Whether it can be mass-produced reliably is almost equivalent to whether CoPoS will succeed.

On the timeline, TSMC set up a R&D production line at its subsidiary VisEra in 2025. 2026 is a critical year for material and equipment verification, with the earliest completion in June; 2027 enters trial production; and mass production is expected from the second half of 2028 to 2029. This means that CoPoS’s truly large-scale shipments are still at least three years away.