SemiAnalysis: Google's next-generation TPU will use Intel's EMIB-T packaging

On July 1, according to renowned semiconductor analysis firm SemiAnalysis, Google's next-generation TPU, codenamed Humufish, will abandon TSMC's CoWoS packaging and instead adopt Intel's EMIB-T technology.

Currently, TSMC's CoWoS is the industry default standard for AI chip packaging. As a leading tech giant, if Google's flagship product successfully migrates to Intel's packaging system, it will impact TSMC. SemiAnalysis stated on X platform:

"Google's next-gen TPU, codenamed Humufish, will use Intel EMIB-T instead of TSMC CoWoS. CoWoS is the industry default, and that's exactly why a flagship component shifting to another solution is noteworthy."

The core difference between the two lies in the physical path of packaging. CoWoS places all dies on a large silicon or RDL interposer. Intel's EMIB technology, on the other hand, embeds small silicon bridges directly into the organic substrate, bridging only where chip-to-chip connections are needed.

Breaking Free from Reticle Limits and Reducing Costs

TSMC's CoWoS silicon interposer is printed using lithography, so its physical size is strictly limited by the reticle limit.

SemiAnalysis explains: "The monolithic version (CoWoS-S) has a limit of about 3.3 times the reticle size, which is why TSMC moved to CoWoS-L. EMIB is not constrained by the reticle limit, making it a much more scalable technology."

Beyond size breakthroughs, cost and efficiency are another core driver. EMIB completely eliminates the expensive interposer, significantly reducing packaging costs.

A more intuitive difference lies in silicon utilization efficiency. Wafers are circular; if you cut large interposers from them, the edge areas generate significant waste, and larger sizes mean lower yields. It's like cutting large square pieces from a round piece of dough—lots of scraps are inevitable.

In contrast, SemiAnalysis says: "Tiny silicon bridges can be densely arranged with almost no waste." Additionally, this choice gives buyers a second supplier beyond TSMC.

Vertical Power Delivery Enhances EMIB-T for Next-Gen HBM

Humufish specifically uses EMIB-T technology, where the "T" stands for Through-Silicon Via (TSV). This design solves power delivery pain points in traditional packaging.

SemiAnalysis explains that ordinary EMIB has no vias in the silicon bridge, so power must bypass it through the substrate, putting pressure on power delivery. "EMIB-T routes power vertically directly through the silicon bridge and adds capacitors and ground planes to deliver cleaner power."

This architectural upgrade is precisely to enable the chip to adapt to next-generation HBM (High Bandwidth Memory) and higher bandwidth interconnect requirements.

Architecture Adaptability and Mass Production Test

Addressing market discussions about TSMC's CoWoS-L also using local silicon bridges, independent industry analyst Nutty pointed out that CoWoS-L adds a global RDL layer on top of the silicon bridge structure. While this improves wiring flexibility, it also increases area and process complexity.

"For chips like Humufish that seem optimized for inference and agent workloads, data flows may be more structured," Nutty analyzed. "In such cases, EMIB's approach of placing high-density links only where needed is more reasonable than paying for full-package wiring flexibility."

Nutty believes this is exactly why EMIB-T is significant. It not only reduces silicon usage and packaging costs but also serves as a second supplier outside the constrained CoWoS ecosystem.

Mass Production Yield Becomes Key, Intel Faces Execution Test

Despite the attractive architecture, execution remains the biggest unknown. Netizen Axi bluntly stated: "Show us the yields before bragging about cost savings."

SemiAnalysis warns: "Ordinary EMIB has been shipping in volume for years, but EMIB-T is new technology. Power-delivering silicon bridges are more difficult to scale in manufacturing."

These advantages can only materialize if Intel can ramp up yields and production as planned. If Intel's progress is delayed, Google's fallback plan remains the capacity-constrained CoWoS. The success or failure of this technology migration will directly test Intel's actual delivery capability in advanced packaging.

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