Samsung Electronics Pushes Next Generation HBM Structural Change… Files Novel Patent for High Stack Response

Samsung Electronics has been confirmed to have filed a new patent aimed at solving the reliability problems of high bandwidth memory (HBM) packages. As the high stack era of HBM4E and HBM5 draws near, the company is innovating the "dummy die" structure that protects the memory dies, pursuing both structural stability and yield stability. According to the HBM packaging patent disclosed on the 28th, Samsung Electronics has developed a technology that machines the side of the topmost dummy die in the stack into a three tier stepped plus curved structure. It is a method that can effectively improve the chip delamination, cracking, and warpage problems that commonly occur in high stack HBM.
HBM is a structure in which multiple memory dies are vertically stacked on top of a base die, with a topmost dummy die placed above them. The dummy die brings the overall package height into specification and performs mechanical protection and heat dissipation roles. However, as the number of stacked layers has climbed beyond 12 to 16 or more, the reliability of the topmost dummy die has emerged as a key variable for yield and long term stability. Typically, the move from 8 to 12 layers cuts yield by 10 to 20 percentage points, and as it goes toward 16 layers it falls more sharply, dropping into the 40 to 60 percent range. Here, improving the dummy die structure addresses the warpage problem and the thermal expansion mismatch problem, which are among the important causes of yield decline.
Samsung Electronics employs a "deep groove sawing" process for the dummy die. Deep groove sawing is a high precision cutting process that separates chips (dies) by carving deep grooves into the wafer, a technique that forms deeper and more precise grooves than conventional ordinary blade sawing (mechanical sawing). Its advantage is that it is laser based and minimizes damage to the semiconductor crystal structure.
This structure is designed in an inverted pyramid form, in which the bottom surface (bonding surface) of the topmost dummy die is kept narrow while the top surface widens. The sides are divided into first, second, and third sides, characterized by a discontinuous structure in which the slope changes abruptly at each connection point, along with a convex curved surface toward the top. As a result, mechanical strength is expected to improve substantially versus a conventional simple vertical side. In addition, by forming a trench (Tr) in advance in the non bonding region (NBR), the design resolves the problem of debris generated during the sawing process contaminating the bonding interface. This in turn strengthens fusion bonding reliability.
It is also noteworthy from a heat management standpoint. The patent precisely designs the vertical distance between the bottom surface of the bonding insulation layer and the horizontal extension surface to be 1 to 10 micrometers, allowing heat transfer efficiency to be maintained at the existing level. A modified protruding surface design that minimizes molding layer (EMC) volume is also included, raising the possibility of actually improving the heat transfer path.
Samsung Electronics appears set to link this technology with existing HBM packaging technologies such as hybrid bonding and HPB (Heat Path Block) to strengthen comprehensive reliability competitiveness and expand its HBM market share.
An industry official explained that in high stack HBM of 12 layers or more, the warpage of the topmost dummy die is in fact a key variable with a major impact on yield, adding that it appears to be a forward looking technology targeting HBM5 of 16 layers or more.