Mars Finance News, on June 23, analyst Damnang stated in an article published on June 22 that the newly released JEDEC SPHBM4 standard is not about making DRAM itself faster, larger, or cheaper, but about changing the connection method between HBM and GPUs. Traditional HBM4 requires connecting to the GPU through a silicon intermediary layer, whereas SPHBM4 attempts to bypass the silicon intermediary layer and connect directly to organic package substrates. The core technology of SPHBM4 is to reuse the DRAM stacking from HBM4, only redesigning the bottom-most base die. Traditional HBM4 has 2,048 data signal pins and relies on the silicon intermediary layer to handle extremely dense connection pitches; SPHBM4 reduces the pin count to 512 and increases single-pin speed fourfold through 4:1 serialization, theoretically maintaining nearly the same total bandwidth as HBM4. Damnang believes that the key of this standard is not "cheaper HBM," but freeing up advanced packaging capacity. Although HBM is expensive and in short supply, the silicon intermediary layer and CoWoS are also significant bottlenecks in AI accelerator shipments. If HBM no longer occupies the area of the intermediary layer, the same wafer capacity of the intermediary layer could support more packages. The article estimates that in high-end AI accelerators, HBM may occupy nearly half of the silicon intermediary layer area. Removing this portion could theoretically increase the number of packages supported per wafer by 1.5 to 2 times. However, the actual effect still depends on adoption rate, yield, product configuration, and remaining GPU-side intermediary layer area. Therefore, SPHBM4 truly releases capacity, not the cost per chip. Even if similar technology can save 22% to 40% of packaging costs, in the total cost of an AI accelerator, it only accounts for a single-digit percentage. Compared to saving hundreds of dollars per chip, a more important benefit is that once the shipment bottleneck is alleviated, GPU and ASIC production volumes could increase. The beneficiaries may not be immediately obvious. In the short term, even if a cloud provider or chip company adopts SPHBM4 first, the released CoWoS capacity might be redistributed by TSMC to queued customers, and NVIDIA may still be the most capable of absorbing the additional capacity. For cloud vendors developing their own ASICs, the value of SPHBM4 is more long-term: reducing dependence on large-area silicon intermediary layers and increasing design and shipment flexibility. The value chain will also shift accordingly. Damnang states that SPHBM4 will shift technological burdens from substrates and silicon intermediary layers to high-speed logic design of the base die. Because increasing single-pin speed makes PHY, SerDes, clock recovery, equalization, and error correction circuits more important. The focus of HBM competition may shift from "who can stack higher" to "who can optimize the underlying logic better." At the company level, Samsung, with its integrated capabilities in memory, advanced logic process, and packaging, has a vertical integration advantage; SK Hynix and Micron rely more on TSMC's advanced nodes to realize complex base dies; TSMC, even with a reduced intermediary layer area, still controls CoWoS and base die foundry services; Intel, with EMIB, high-speed interconnects, and advanced packaging capabilities, remains a potential variable. However, SPHBM4 is currently still in the "standard release, awaiting adoption" stage. The next steps to watch are: which memory manufacturer will launch SPHBM4 products first, whether large cloud providers will incorporate this design into their self-developed ASICs, and whether JEDEC will publish complete technical details. Damnang is a long-term analyst focused on the semiconductor and AI infrastructure industries. His Substack mainly publishes analysis of the semiconductor, memory, advanced packaging, wafer foundry, and AI chip supply chain, characterized by breaking down complex engineering issues into industry logic that investors can understand.

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Analyst: HBM packaging route changes, SPHBM4 may push AI chip bottlenecks to the underlying chips

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