SanDisk patent exposes a 3D storage-and-compute architecture: coordinated layered collaboration between HBM and NAND

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Mars Finance News, June 22 — SanDisk recently disclosed a patent showing that the company has proposed a 3D stacking architecture based on CBA storage chips: integrating GPU or AI accelerators and other computing chips directly onto NAND/CMOS logic storage units, placing them in an intermediary layer, with HBM chips stacked around them. The HBM is responsible for high-bandwidth, low-latency access, while the NAND layer handles large-capacity read/write and storage tasks.
This design aims to address the capacity limitations of HBM (approximately 32–64GB per stack). Previously, SanDisk proposed the HBF architecture, which stacks NAND vertically using TSVs, achieving capacities of up to 4TB, an 8–16 times increase over HBM, but still facing challenges related to latency and system integration complexity.
Compared to DRAM, NAND offers higher capacity and lower cost but slower access speeds. The new architecture achieves a perfect complement of both through 3D layering. (Titan Garage)
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