SemiAnalysis Breaks Down Huawei Kirin 9030: The Process Technology Can't Keep Up, Folding the Chip

Writing: Trend Research

In the field of semiconductor reverse engineering, TechInsights has dominated for decades. Last weekend, Dylan Patel's SemiAnalysis officially released its first public teardown report from its STEEL (Teardown Engineering & Evaluation Lab), targeting one of the most closely watched chips worldwide, Huawei's Mate 80 Pro equipped with the Kirin 9030 Pro, manufactured with SMIC's most advanced N+3 process.

The timing is intriguing. TechInsights is being sold through private equity, while SemiAnalysis's revenue has already surpassed that of this longstanding giant. Dylan chose this moment to strike with a highly technical teardown report, accompanied by real chip photos from the Oregon lab.

The report's title is a bombshell: SMIC's N+3 process has a minimum metal pitch (M0 pitch) of only 32.5nm, smaller than Intel's latest Panther Lake processor using the 18A process at 36nm.

SMIC, without EUV lithography tools, has achieved a finer metal pitch than Intel?

If you only look at the headline, this news could blow up the entire semiconductor industry, but SemiAnalysis itself dampened expectations in the second paragraph of the report, calling it a "cherry-picked metric," a deliberately selected indicator.

This article will interpret this teardown report for you,

Density matched, at a high cost

SMIC's N+3 process indeed matches TSMC's N6 in transistor density.

STEEL's lab used TEM (Transmission Electron Microscope) cross-sectional analysis, measuring the Bohr density of N+3 at 113.4 MTr/mm², slightly higher than TSMC's N6 at 107.7 MTr/mm². The cell height shrank from 252nm in N+2 to 228nm, and the contact gate pitch (CGP) reduced from 63nm to 57nm. Taken together, these figures mean SMIC, without EUV, has achieved logic density comparable to TSMC's mature 7nm level through pure DUV lithography.

What is the cost?

SMIC's M0 layer uses Self-Aligned Quadruple Patterning (SAQP), which involves four processing steps on a single mask to achieve finer lines. TSMC's N6 on the same layer only requires double patterning (SADP). Quadruple patterning means more masks, higher overlay accuracy requirements, more complex processes, and higher costs.

SemiAnalysis directly observed the cost of SAQP in the cross-sectional images: the M0 trench of N+3 shows a clear inverted trapezoid profile (narrower at the bottom), with a distinct barrier layer enrichment at the trench bottom. While this morphology helps copper fill, at a 32.5nm pitch, process control becomes extremely challenging.

To use a metaphor understandable to a trader: SMIC is producing the same denomination of banknotes, but each note costs several times more to print than TSMC's, with higher yield risks. Same density, entirely different economics.

Kirin 9030: squeezing every inch of silicon under constrained conditions

Huawei HiSilicon's chip design capability is a story on another level.

In terms of chip area, the Kirin 9030 is nearly the same size as the previous 9020 (about 140mm²), but packed with more features: the CPU upgraded from 1 big core + 3 medium cores to 1 big + 4 medium cores; GPU compute units increased from 4 to 6; the NPU gained an additional Tiny core; cache levels expanded across the board. The density boost from N+3 allows Huawei to fit more logic units into the same chip size.

Performance-wise, STEEL's report cites public benchmark data, giving a clear positioning: the GPU performance (Maleoon 935) of Kirin 9030 roughly matches flagship levels from 2022, with a 3DMark WLE score up 70% over the previous generation, slightly surpassing Snapdragon 8+ Gen 1, but lagging behind the current flagship Snapdragon 8 Elite Gen 5 by a factor of 2.4 to 2.6.

The CPU situation more clearly illustrates the point. The big core TaiShan Prime's per-clock performance (IPC) is roughly on par with Arm Cortex-X2, a design from 2021. Apple's 2020 M1 Firestorm core still outperforms by 35% in IPC. The latest Apple M5 P core exceeds IPC by 60%, with absolute performance 2.7 times higher.

The root of the gap isn't in design but in process technology. Apple and Qualcomm use TSMC's N4 and N3P processes, which have inherent advantages in voltage-frequency curves: more transistors per area, higher possible frequencies at the same power, and better efficiency. Huawei's core design level is comparable to industry-leading previous generations but is constrained by two generations old manufacturing processes.

When process scaling stalls, Huawei plans to "fold"

The most forward-looking part of the report is Huawei's τ scaling law and LogicFolding roadmap announced at the 2026 ISCAS conference.

Traditional semiconductor scaling advances in two dimensions: shrinking transistors and fine-tuning metal lines. Moore's Law has been doing this for decades. Huawei now proposes τ scaling, shifting the optimization goal from spatial to temporal domain, focusing on reducing data movement and processing time costs, including transistor switching delay, signal propagation delay, and compute and storage latency.

LogicFolding is the engineering implementation of this theory. Simply put, it involves splitting a logical module into two layers stacked face-to-face, connected via ultra-fine pitch hybrid bonding. The direct benefit is shortening the longest signal path. In modern chips, a large portion of power and delay is spent on driving long interconnects and buffers. Vertically folding logic shortens critical paths, enabling higher frequencies and lower power consumption.

Huawei presents an aggressive roadmap: the big core of Kirin 9030 runs at 2.75GHz, with test chips already running at 3.39GHz, aiming for 5GHz by 2031, while using 3D stacking to push the effective density to 295 MTr/mm², comparable to TSMC's 14A level.

SemiAnalysis remains cautious. They note that Huawei's density calculation differs from traditional foundries: the 3D stacking density is based on package area, stacking multiple active logic layers, which naturally yields higher numbers. If applying the same method to AMD's MI450X (N2 top + N3P bottom), the theoretical density could reach 460.2 MTr/mm², far exceeding Huawei's 2031 target.

But the direction itself is worth noting. Huawei's approach essentially shifts the role of the foundry to the system design company under process constraints. AMD's V-Cache stacks cache in 3D, and MI350X moves IO and interconnect to the bottom chip; Huawei aims to go further, splitting the same logic block into vertical distributed parts—another level of engineering challenge.

Export controls reshape the dimensions of competition

SemiAnalysis's final conclusion is straightforward: export controls haven't stopped China's chip progress but have changed its path and costs.

SMIC's N+3 demonstrates that achieving N6 logic density without EUV is possible. But this path is more costly, more complex, and with lower yields. Each step downward increases marginal difficulty: more masks, stricter overlay, more expensive multi-patterning. Theoretically, N+4 could reach 137.8 MTr/mm² (comparable to TSMC's N5), and N+5, with backside power delivery, could approach Intel's 18A HP library. But each step is more difficult, more expensive, and less tolerant of errors.

Meanwhile, SMIC's N+2 and N+3 processes are shifting toward Huahong, with design firms like Alibaba Pingtouge and Cambrian potentially benefiting. Knowledge of chip manufacturing is spreading from single foundries to ecosystems, further diluting the effectiveness of sanctions targeting individual companies.

On the design side, Huawei and Peking University are developing domestic EDA tool prototypes for LogicFolding. While not replacing the full toolchains of Synopsys and Cadence, domestic EDA is evolving toward "architecture-process-package co-optimization."

An interesting detail: SemiAnalysis found that the Kirin 9030 Pro's DRAM is from Samsung (K4L2E165YD, LPDDR5X-9600, 1a process node), and the 16GB Pro Max version features packages from both Samsung and Changxin Memory (CXMT). Changxin's chip package date is marked as week 45 of 2025, with process density comparable to industry 1z nodes. This indicates that Chinese memory chips are beginning to enter Huawei's flagship supply chain, even though their process lags behind Samsung and SK Hynix by one or two generations.

For investors, the real signal to watch is whether Huawei's 3D stacking roadmap can make Chinese chips sufficiently capable in smartphones, AI inference, and network equipment at manageable costs.

If this "good enough" threshold is reached, the strategic value of this supply chain will be re-priced.