AMD is trying to code its way past CUDA by handing the ISA to the models.

The move: publish the GPU instruction set in a machine-readable spec so a frontier model can generate ROCm kernels straight from it.
> CUDA's real lock-in was never the hardware, it was 15+ years of hand-tuned kernels and libraries
> AMD can't out-write that by hand, so it wants LLMs to write the kernel layer instead
> Machine-readable ISA is the input those models need to do it reliably
Whether the generated kernels actually hit performance parity is the open question. But the strategy is clear: attack the software moat, not the silicon.