Huawei apresenta a "Lei de Tao" de semicondutores, substituindo a dimensão temporal pela geometria, o processador Kirin de Q3 adota totalmente o dobramento lógico

Huawei Semiconductor Business Unit President He Tingbo officially announced the "Tao (τ) Law" at the 2026 International Circuit and System Symposium, proposing to replace geometric scaling with temporal miniaturization, continuously compress signal propagation delays through logic folding technology, becoming China's first independently proposed new industry development principle in the semiconductor field. Based on this law, Huawei has successfully designed and mass-produced 381 chips over the past six years; it is expected that by 2031, high-end chip transistor density will reach the same level as 1.4 nanometer process technology.
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• 381 chips in six years, from theory to mass production
• Autumn Kirin chips fully adopt logic folding for the first time
• Multi-level collaborative optimization system and 2031 goals
• Naming of the "Tao (τ) Law" and its strategic implications for China's semiconductor industry

Huawei's Director and President of the Semiconductor Business Unit, He Tingbo, delivered a keynote speech titled "Exploration and Practice of New Paths in Semiconductors" at the 2026 International Circuit and System Symposium (ISCAS 2026) held in Shanghai on the 25th, officially proposing the "Tao (τ) Law." This is the first time China has independently proposed a guiding principle for industry development in the global semiconductor field, marking a new direction for China's chip technology path from chasing geometric miniaturization to system-level delay compression.

According to People's Daily, the core concept of the "Tao Law" is to replace the decades-long adherence to geometric scaling in the semiconductor industry with "temporal miniaturization," aiming to systematically reduce the time constant (τ) through innovative techniques such as logic folding, continuously compressing signal transmission delays, thereby increasing transistor density and achieving sustainable evolution of semiconductors and electronic systems.

Six years, 381 chips, from theory to mass production

He Tingbo pointed out in his speech that, based on this new principle, Huawei has successfully designed and mass-produced 381 chips over the past six years, covering multiple fields from terminal devices to infrastructure. This figure not only demonstrates Huawei's resilience in maintaining chip R&D capabilities under US sanctions but also reflects that the "Tao Law" has been preliminarily validated through actual product iterations.

These 381 chips include Huawei's HiSilicon product line, such as Ascend AI acceleration chips, Kunpeng server processors, and Kirin mobile chips. Against the backdrop of tightening US export controls, Huawei is gradually establishing a non-US chip design and manufacturing supply chain, and the "Tao Law" is the technical theoretical foundation of this strategy.

Autumn Kirin chips fully adopt logic folding for the first time

He Tingbo also previewed that Huawei will release a new generation Kirin mobile chip this autumn, fully adopting logic folding technology to significantly enhance performance. Logic folding is one of the important practical implementations of the "Tao Law," which reorganizes the internal logic unit layout and interconnection structure of the chip, achieving performance and power optimization without relying on advanced process miniaturization.

It is noteworthy that this means the new Kirin chips may no longer depend on the most advanced nanometer processes (such as 3nm or below), but instead compensate for process limitations through architectural innovation. This has profound implications for the global semiconductor industry—if logic folding technology can be validated through mass production, it will open a new technical pathway for chip designers restricted by EUV exposure equipment export controls.

Multi-level collaborative optimization system and 2031 goals

The "Tao Law" constructs a multi-level collaborative optimization system spanning components, circuits, chips, and systems. Unlike the traditional Moore's Law, which solely pursues transistor line width reduction, the "Tao Law" approaches from the perspective of system-level time constants, seeking cross-layer delay optimization.

He Tingbo expects that by 2031, high-end chips based on this law will reach the same level as 1.4 nanometer process technology in transistor density. This indicates Huawei's confidence in this technological route and sets a clear technical milestone for chip R&D over the next five years.

Naming of the "Tao (τ) Law" and its strategic implications for China's semiconductor industry

The character "Tao" is directly taken from He Tingbo's name, also implying strategy and planning as in "literary and martial strategies." The Greek letter τ (tau) is commonly used in physics to denote the time constant, echoing the law's focus on delay compression.

This naming approach is similar to Moore's Law, named after its founder Gordon Moore, highlighting Huawei's and China's attempt to establish independent technological discourse. In the current context of global chip supply chain restructuring and US-China technological competition, the proposal of the "Tao Law" is not only a technological declaration but also a symbol of industrial policy and national strategy.