PMI three indices rise simultaneously, with new momentum demand continuing to expand

Securities Times Reporter Wang Yiming

AI computing power has become the starting point for reshaping the chip industry.

In recent years, as Moore’s Law has slowed down and the performance of a single chip has been unable to meet the explosive demand for computing power, the global industry has evolved two avenues to break through: advanced packaging and system-level integration of supernode architectures. Against this backdrop, every link in China’s domestic chip industry chain—including EDA (electronic design automation), advanced packaging, semiconductor equipment, and high-speed interconnect technologies—has been accelerating its layout in the AI computing power field.

When discussing domestic industry trends, Wang Xiaolong, director of the business department at Chips Research, told Securities Times reporter Wang Yiming that with China’s strategy of independent and controllable semiconductor development being pushed deeper, although the process node is constrained to some extent, the domestic industry chain can still carve out a semiconductor development path with Chinese characteristics through “appropriate process nodes + advanced packaging + system and ecosystem optimization.” This is expected to reduce the structural disadvantages and systemic risks China faces in competition for the next round of AI and advanced computing industries.

EDA competition shifts to system-level integration

As the top-most layer in the chip industry, EDA practitioners feel the trend of AI reshaping the chip design industry quite deeply.

“From multi-chip particles to supernodes, system-level complexity has been unprecedented. In the AI hardware domain, customers no longer face a challenge of designing a single chip; instead, they face system-level risks brought by Chiplet advanced packaging, heterogeneous integration, high-bandwidth memory, ultra-high-speed interconnects, efficient power networks, and AI data center architectures. This includes systemic issues such as whole systems overheating, warping, and bowing due to insufficient attention to heat dissipation; power network design defects causing fuse failures at the packaging connection points under high load; and the inability to light up tens of millions of dollars worth of tape-outs after assembly due to a lack of a system-level signal management perspective.” Ling Feng, founder and chairman of Chips and Semiconductors, said at a press conference earlier this month.

Ling Feng noted that to solve the above problems, EDA vendors need to establish the “system-level integration and coordination (STCO)” concept, achieving coordinated design across computing, networking, power delivery, cooling, and system architecture.

The three global EDA giants have verified industry trends with real acquisitions backed by hard cash. In 2025, Synopsys Tech acquired Ansys, the world’s largest simulation EDA company, for $35 billion, filling out multi-physics field simulation capabilities and strengthening end-to-end analysis capability from chip to system.

Domestic AI chip makers are also actively laying out and investing at the ecosystem level. Sun Guoliang, senior vice president and chief product officer of Moore Emerge (Cement Technologies), recently said at the SEMICON forum that Moore Emerge has built a complete GPU product matrix under a unified self-developed architecture, covering scenarios such as AI training, inference, graphic rendering, and scientific intelligence. Its accompanying self-developed software stack is fully compatible with the mainstream ecosystem, and it is also actively promoting the development of open-source ecosystems.

In Wang Xiaolong’s view, a good software ecosystem is crucial to improving hardware utilization efficiency, which will accelerate the process of domestic AI chips moving from “being replaceable and workable” to “being independently usable and truly effective.” For example, behind the mainstream breakthrough of domestic large models such as DeepSeek and Qianwen, domestic AI chips have made a major improvement in utilization efficiency.

Hybrid bonding boosts computing power: core technology

At the hardware level, in the era of massive AI computing power, when a single chip faces three major bottlenecks—power consumption, area, and yield—advanced packaging has become the new “carrier” of a “new Moore’s Law.” Taking TSMC’s CoWoS as an example, each generation integrates more GPUs, larger HBM (high-bandwidth memory), and stronger interconnects. Currently, AI chip giants including Nvidia and AMD have achieved cross-tier improvements in AI chip computing power through advanced packaging technologies.

At this year’s SEMICON forum, Guo Xiaochao, market director for the foundry business division at Wuhan Xinxin Integrated Circuit Co., Ltd., discussed the latest industry trends. He pointed out that the advanced packaging market, especially in the 2.5D/3D领域, is expanding rapidly. Mainstream industry solutions have evolved from CoWoS-S to CoWoS-L, SoW, and 3.5D XDSiP. Integration scale continues to grow. Hybrid bonding is the key to achieving high-density interconnects and also the core technology for improving computing power. This not only requires process breakthroughs, but also demands joint efforts in design methodologies, materials, and equipment.

In terms of domestic equipment, Northern Engineering (002371) recently released a 12-inch chip-to-wafer (D2W) hybrid bonding tool. It is understood that the equipment focuses on the extreme interconnect requirements across the full scope of 3D integration applications such as SoC, HBM, and Chiplet, breaking through key process challenges including lossless pickup of micrometer-class ultra-thin chips, nano-level ultra-high precision alignment, and stable bonding with no voids and high quality. It achieves a better balance between nano-level alignment accuracy and high-speed bonding production capacity, becoming the first domestic supplier to complete client-side process validation for D2W hybrid bonding equipment.

Topsun Technology also launched a 3D IC series at the SEMICON forum, covering multiple new products such as fused bonding and laser debonding, with a focus on Chiplet heterogeneous integration, three-dimensional stacking, and HBM-related applications.

In recent years, hybrid bonding equipment has become the fastest-growing sub-segment within semiconductor equipment. Yole, a market consulting firm, predicts that by 2030, its global market size will exceed $1.7 billion. The expected CAGR for D2W hybrid bonding equipment is as high as 21%.

However, relevant executives at large semiconductor equipment companies also noted that although the hybrid bonding equipment market is growing rapidly, it also faces challenges such as alignment precision, clean-environment requirements, and warpage tolerance/containment. Meanwhile, different application scenarios for hybrid bonding require different interface material selections. The combination of dielectric materials such as SiCN (amorphous-state materials) with copper each has its own pros and cons. Surface morphology, particle control, and wafer warpage directly affect bonding yield. Three-dimensional integration depends on close cooperation across the industry.

Supernode technology体系 white paper released

Another path to break through AI computing power expansion is supernode system integration. Using high-speed interconnect technologies, the computing units can be expanded from single-node and rack-level supernodes (hundreds of AI chips) to cluster-level supernodes (tens of millions of AI chips). By combining supernodes with advanced packaging, a “supercomputer” is formed, consisting of large numbers of AI chips, HBM, high-speed interconnect networks, and liquid-cooling heat dissipation systems.

Domestic big manufacturers also have innovations and deployments in the supernode field. On March 26, Inspur (603019) unveiled the world’s first wireless cable rack-based supernode scaleX40 at the annual conference of the Zhongguancun (000931) forum. It is said that traditional supernodes rely on fiber optics and copper cable interconnects, and typically suffer from pain points such as long deployment cycles, complex maintenance complexity, and numerous failure points. scaleX40 adopts an orthogonal wireless cable first-level interconnect architecture, enabling direct plug-in connections between computing nodes and switch nodes, fundamentally eliminating performance loss and operational risks caused by cables.

The scaleX40 integrates 40 GPU cards per single node, with total computing power exceeding 28 PFlops. Total HBM total visible memory exceeds 5TB, and the total memory access bandwidth exceeds 80TB/s, forming high-density computing units that meet training and inference requirements for trillion-parameter large models.

Li Bin, senior vice president of Inspur, said the significance of scaleX40 is not only improving performance, but also reconstructing the logic of how computing power is delivered—pushing computing power from “engineering-based construction” toward “productized supply,” greatly lowering the entry barrier and deployment cost for high-end computing power.

At the industry level, on March 29, the “Supernode Technology System White Paper” (hereinafter referred to as the “White Paper”), jointly completed by Shanghai AI Laboratory together with AI industry-chain companies across upstream and downstream such as Qisimoer, Moore Emerge, and Jietiao Xingchen, was officially released. The White Paper aims to address core pain points for large-scale deployment of supernodes, such as hard-to-achieve heterogeneous coordination, low cross-domain scheduling efficiency, and complex engineering deployment, providing theoretical guidance from the perspective of industry practice.

Qisimoer believes that in the future, the value of supernodes will be reflected more in whether it can organize computing, storage, interconnection, scheduling, and runtime resources into a unified coordinated system unit, while maintaining high bandwidth, low latency, high utilization, and sustainable scalability at larger scales. Supernodes are no longer just “a combination of more acceleration chips,” but a new architectural unit that determines whether the system can maintain effective coordination under large-scale conditions.

(Editor: Dong Pingping)

     【Disclaimer】This article only represents the author’s own views and is not related to Hexun. The Hexun website maintains neutrality toward the statements and judgment of views in the text, and provides no express or implied guarantee regarding the accuracy, reliability, or completeness of the content included. Readers are requested to use this information only as a reference and bear all responsibility themselves. Email: news_center@staff.hexun.com

Report