Cost reduced to one percent! This domestically produced chip achieves a significant breakthrough

Ask AI · How does Hu Huiyong’s team overcome the lattice mismatch problem of silicon-germanium?

On March 30, the reporter learned from Xi’an University of Electronic Science and Technology that Professor Hu Huiyong’s team successfully developed a single-photon avalanche diode (SPAD) chip based on silicon-germanium technology, significantly reducing the manufacturing cost of short-wave infrared detection technology. This breakthrough could enable high-end chips, which normally cost thousands of dollars each, to enter fields such as smartphones and automotive lidar at a cost of just one percent.

Short-wave infrared technology has the ability to penetrate haze and fog, providing clear imaging in darkness, and can also identify material characteristics of different substances. It has broad prospects in smartphone low-light photography, automotive lidar, industrial nondestructive testing, and other fields. However, for a long time, mainstream solutions mainly used indium gallium arsenide materials, which, despite excellent performance, are limited by expensive indium phosphide substrates, making it difficult to be compatible with silicon-based CMOS (complementary metal-oxide-semiconductor) processes. As a result, individual chips often cost hundreds to thousands of dollars.

Hu Huiyong’s team chose a technology route highly compatible with the existing semiconductor industry chain—silicon-germanium. They utilized the silicon-germanium epitaxial growth process platform to produce the material, and then used standard silicon-based CMOS process platforms to fabricate the detector devices, extending the detection range into the short-wave infrared band. “This means we are using the cost of making smartphone chips to produce short-wave infrared detectors that used to only be possible at ‘sky-high’ prices,” said Wang Liming.

Silicon-germanium dedicated wafer fabrication line. Photo provided by interviewee.

However, there is a 4.2% lattice mismatch between the atomic arrangements of silicon and germanium, which can cause material defects and detector leakage currents. This has prevented the technology from moving out of the laboratory for over 20 years. To overcome this challenge, the team worked on multiple fronts simultaneously: designing multi-layer gradient buffer layers combined with low-temperature growth techniques to gradually reduce atomic mismatch; using in-situ annealing and passivation techniques to suppress leakage; and innovating SPAD structural designs to optimize electric field distribution, making signals clearer and noise lower.

Today, the team has established an autonomous full-chain R&D capability covering “device design—material epitaxy—wafer fabrication—circuit matching—system verification.” The dedicated silicon-germanium wafer fabrication line, currently under construction, is expected to be completed by the end of 2026, providing rapid validation and controllable production capacity for subsequent product iterations.

Source: Science and Technology Daily